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Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which

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is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-08-30 22:05:23 +00:00
parent 17f9bfaa83
commit 55c134a261
2 changed files with 2 additions and 69 deletions
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21
lib/Target/ARM/ARMInstrFormats.td
View File

@ -1148,22 +1148,6 @@ class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
list<Predicate> Predicates = [IsThumb2];
}
// Same as Thumb2sI except it does modify CPSR. Note it's modeled as an input
// operand since by default it's a zero register. It will become an implicit def
// once it's "flipped".
// FIXME: This uses unified syntax so {s} comes before {p}. We should make it
// more consistent.
class Thumb2sI_cpsr<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p, s_cc_out:$s));
let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
let Pattern = pattern;
list<Predicate> Predicates = [IsThumb2];
}
// Special cases
class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
InstrItinClass itin,
@ -1219,11 +1203,6 @@ class T2sI<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
class T2sI_cpsr<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: Thumb2sI_cpsr<oops, iops, AddrModeNone, Size4Bytes, itin, opc,
asm, "", pattern>;
class T2XI<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;

50
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -249,57 +249,12 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
}
}
/// T2I_bin_cpsr_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for
/// a binary operation that produces a value. These are predicable and modify
/// CPSR.
multiclass T2I_bin_cpsr_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0, string wide = ""> {
// shifted imm
def ri : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs),
IIC_iALUi, opc, "\t$dst, $lhs, $rhs",
[(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
let Inst{20} = 1; // The S bit.
let Inst{15} = 0;
}
// register
def rr : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs),
IIC_iALUr, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
[(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
let Inst{20} = 1; // The S bit.
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
}
// shifted register
def rs : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs),
IIC_iALUsi, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
[(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
let Inst{20} = 1; // The S bit.
}
}
/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
// the ".w" prefix to indicate that they are wide.
multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> :
T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
/// T2I_bin_sw_irs - Same as T2I_bin_w_irs except these operations set
// the 'S' bit.
multiclass T2I_bin_sw_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> :
T2I_bin_cpsr_irs<opcod, opc, opnode, Commutable, ".w">;
/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
/// reversed. The 'rr' form is only defined for the disassembler; for codegen
/// it is equivalent to the T2I_bin_irs counterpart.
@ -1680,9 +1635,8 @@ defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
//let Defs = [CPSR] in
defm t2ANDS : T2I_bin_sw_irs<0b0000, "and",
BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>;
defm t2ANDS : T2I_bin_s_irs<0b0000, "and",
BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>;
let Constraints = "$src = $dst" in
def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),