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Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this out! :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1148,22 +1148,6 @@ class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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list<Predicate> Predicates = [IsThumb2];
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}
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// Same as Thumb2sI except it does modify CPSR. Note it's modeled as an input
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// operand since by default it's a zero register. It will become an implicit def
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// once it's "flipped".
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// FIXME: This uses unified syntax so {s} comes before {p}. We should make it
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// more consistent.
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class Thumb2sI_cpsr<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ins pred:$p, s_cc_out:$s));
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let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb2];
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}
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// Special cases
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class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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InstrItinClass itin,
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@ -1219,11 +1203,6 @@ class T2sI<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
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class T2sI_cpsr<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb2sI_cpsr<oops, iops, AddrModeNone, Size4Bytes, itin, opc,
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asm, "", pattern>;
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class T2XI<dag oops, dag iops, InstrItinClass itin,
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string asm, list<dag> pattern>
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: Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
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@ -249,57 +249,12 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
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}
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}
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/// T2I_bin_cpsr_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for
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/// a binary operation that produces a value. These are predicable and modify
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/// CPSR.
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multiclass T2I_bin_cpsr_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0, string wide = ""> {
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// shifted imm
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def ri : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs),
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IIC_iALUi, opc, "\t$dst, $lhs, $rhs",
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[(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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let Inst{20} = 1; // The S bit.
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let Inst{15} = 0;
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}
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// register
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def rr : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs),
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IIC_iALUr, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
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[(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
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let isCommutable = Commutable;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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let Inst{20} = 1; // The S bit.
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let Inst{14-12} = 0b000; // imm3
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let Inst{7-6} = 0b00; // imm2
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let Inst{5-4} = 0b00; // type
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}
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// shifted register
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def rs : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs),
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IIC_iALUsi, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
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[(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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let Inst{20} = 1; // The S bit.
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}
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}
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/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
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// the ".w" prefix to indicate that they are wide.
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multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> :
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T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
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/// T2I_bin_sw_irs - Same as T2I_bin_w_irs except these operations set
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// the 'S' bit.
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multiclass T2I_bin_sw_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> :
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T2I_bin_cpsr_irs<opcod, opc, opnode, Commutable, ".w">;
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/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
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/// reversed. The 'rr' form is only defined for the disassembler; for codegen
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/// it is equivalent to the T2I_bin_irs counterpart.
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@ -1680,9 +1635,8 @@ defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
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defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
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BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
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//let Defs = [CPSR] in
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defm t2ANDS : T2I_bin_sw_irs<0b0000, "and",
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BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>;
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defm t2ANDS : T2I_bin_s_irs<0b0000, "and",
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BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>;
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let Constraints = "$src = $dst" in
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def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
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