From 55dabaa73a7a0be4398fae58443f3ad8264e537e Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 27 Oct 2011 22:25:42 +0000 Subject: [PATCH] ARM isel for vld1, opcode selection for register stride post-index pseudos. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143158 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 8a1b618b963..39d4d39c904 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1562,6 +1562,10 @@ static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) { case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register; case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register; case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register; + case ARM::VLD1q8PseudoWB_fixed: return ARM::VLD1q8PseudoWB_register; + case ARM::VLD1q16PseudoWB_fixed: return ARM::VLD1q16PseudoWB_register; + case ARM::VLD1q32PseudoWB_fixed: return ARM::VLD1q32PseudoWB_register; + case ARM::VLD1q64PseudoWB_fixed: return ARM::VLD1q64PseudoWB_register; } return Opc; // If not one we handle, return it unchanged. }