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[x86, dag] Teach the DAG combiner to prune inputs toa vector_shuffle
that are unused. This allows the combiner to delete math feeding shuffles where the math isn't actually necessary. This improves some of the vperm2x128 tests that regressed when the vector shuffle lowering started actually generating vperm instructions rather than forcibly decomposing them. Sadly, this isn't enough to get this *really* right because we still form a completely unnecessary permutation. To fix that, we also need to fold shuffles which just rearrange concatenated or inserted subvectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219086 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -17,6 +17,7 @@
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/Statistic.h"
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@ -10708,6 +10709,92 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
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return SDValue();
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}
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static SDValue simplifyShuffleOperandRecursively(SmallBitVector &UsedElements,
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SDValue V, SelectionDAG &DAG) {
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SDLoc DL(V);
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EVT VT = V.getValueType();
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switch (V.getOpcode()) {
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default:
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return V;
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case ISD::CONCAT_VECTORS: {
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EVT OpVT = V->getOperand(0).getValueType();
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int OpSize = OpVT.getVectorNumElements();
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SmallBitVector OpUsedElements(OpSize, false);
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bool FoundSimplification = false;
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SmallVector<SDValue, 4> NewOps;
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NewOps.reserve(V->getNumOperands());
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for (int i = 0, NumOps = V->getNumOperands(); i < NumOps; ++i) {
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SDValue Op = V->getOperand(i);
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bool OpUsed = false;
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for (int j = 0; j < OpSize; ++j)
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if (UsedElements[i * OpSize + j]) {
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OpUsedElements[j] = true;
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OpUsed = true;
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}
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NewOps.push_back(
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OpUsed ? simplifyShuffleOperandRecursively(OpUsedElements, Op, DAG)
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: DAG.getUNDEF(OpVT));
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FoundSimplification |= Op == NewOps.back();
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OpUsedElements.reset();
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}
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if (FoundSimplification)
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V = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, NewOps);
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return V;
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}
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case ISD::INSERT_SUBVECTOR: {
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SDValue BaseV = V->getOperand(0);
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SDValue SubV = V->getOperand(1);
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auto *IdxN = dyn_cast<ConstantSDNode>(V->getOperand(2));
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if (!IdxN)
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return V;
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int SubSize = SubV.getValueType().getVectorNumElements();
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int Idx = IdxN->getZExtValue();
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bool SubVectorUsed = false;
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SmallBitVector SubUsedElements(SubSize, false);
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for (int i = 0; i < SubSize; ++i)
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if (UsedElements[i + Idx]) {
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SubVectorUsed = true;
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SubUsedElements[i] = true;
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UsedElements[i + Idx] = false;
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}
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// Now recurse on both the base and sub vectors.
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SDValue SimplifiedSubV =
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SubVectorUsed
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? simplifyShuffleOperandRecursively(SubUsedElements, SubV, DAG)
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: DAG.getUNDEF(SubV.getValueType());
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SDValue SimplifiedBaseV = simplifyShuffleOperandRecursively(UsedElements, BaseV, DAG);
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if (SimplifiedSubV != SubV || SimplifiedBaseV != BaseV)
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V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
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SimplifiedBaseV, SimplifiedSubV, V->getOperand(2));
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return V;
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}
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}
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}
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static SDValue simplifyShuffleOperands(ShuffleVectorSDNode *SVN, SDValue N0,
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SDValue N1, SelectionDAG &DAG) {
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EVT VT = SVN->getValueType(0);
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int NumElts = VT.getVectorNumElements();
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SmallBitVector N0UsedElements(NumElts, false), N1UsedElements(NumElts, false);
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for (int M : SVN->getMask())
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if (M >= 0 && M < NumElts)
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N0UsedElements[M] = true;
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else if (M >= NumElts)
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N1UsedElements[M - NumElts] = true;
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SDValue S0 = simplifyShuffleOperandRecursively(N0UsedElements, N0, DAG);
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SDValue S1 = simplifyShuffleOperandRecursively(N1UsedElements, N1, DAG);
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if (S0 == N0 && S1 == N1)
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return SDValue();
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return DAG.getVectorShuffle(VT, SDLoc(SVN), S0, S1, SVN->getMask());
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}
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// Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
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static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
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EVT VT = N->getValueType(0);
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@ -10860,6 +10947,12 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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}
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}
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// There are various patterns used to build up a vector from smaller vectors,
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// subvectors, or elements. Scan chains of these and replace unused insertions
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// or components with undef.
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if (SDValue S = simplifyShuffleOperands(SVN, N0, N1, DAG))
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return S;
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if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
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Level < AfterLegalizeVectorOps &&
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(N1.getOpcode() == ISD::UNDEF ||
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@ -64,11 +64,9 @@ entry:
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define <32 x i8> @Ei(<32 x i8> %a, <32 x i8> %b) nounwind uwtable readnone ssp {
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; AVX1-LABEL: Ei:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
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; AVX1-NEXT: vpaddb %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,2,3]
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; AVX1-NEXT: retq
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;
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@ -87,11 +85,7 @@ entry:
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define <4 x i64> @E2i(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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; AVX1-LABEL: E2i:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1]
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; AVX1-NEXT: vpaddq %xmm3, %xmm2, %xmm2
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; AVX1-NEXT: vpaddq %xmm3, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1]
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; AVX1-NEXT: retq
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;
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@ -111,11 +105,9 @@ entry:
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define <8 x i32> @E3i(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
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; AVX1-LABEL: E3i:
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; AVX1: ## BB#0: ## %entry
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1]
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; AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm2
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; AVX1-NEXT: vpaddd %xmm3, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
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; AVX1-NEXT: retq
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;
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@ -2512,3 +2512,67 @@ define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
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%2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
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ret <4 x float> %2
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}
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; These tests are designed to test the ability to combine away unnecessary
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; operations feeding into a shuffle. The AVX cases are the important ones as
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; they leverage operations which cannot be done naturally on the entire vector
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; and thus are decomposed into multiple smaller operations.
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define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
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; SSE-LABEL: combine_unneeded_subvector1:
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; SSE: # BB#0:
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_unneeded_subvector1:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_unneeded_subvector1:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
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; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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%b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
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%c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
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ret <8 x i32> %c
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}
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define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
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; SSE-LABEL: combine_unneeded_subvector2:
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; SSE: # BB#0:
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
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; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_unneeded_subvector2:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
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; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,2,1,0]
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; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
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; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_unneeded_subvector2:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <7,6,5,4,u,u,u,u>
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; AVX2-NEXT: vpermd %ymm1, %ymm2, %ymm1
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; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
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; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
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; AVX2-NEXT: retq
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%c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
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%d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
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ret <8 x i32> %d
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}
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