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Implement 64-bit undef, sub, shl/shr, srem/urem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28929 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -52,7 +52,8 @@ static unsigned getNumBytesForInstruction(MachineInstr *MI) {
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// minor pessimization that saves us from having to worry about
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// keeping the offsets up to date later when we emit long branch glue.
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return 8;
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case PPC::IMPLICIT_DEF_GPR: // no asm emitted
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case PPC::IMPLICIT_DEF_GPRC: // no asm emitted
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case PPC::IMPLICIT_DEF_G8RC: // no asm emitted
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case PPC::IMPLICIT_DEF_F4: // no asm emitted
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case PPC::IMPLICIT_DEF_F8: // no asm emitted
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return 0;
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@ -125,7 +125,8 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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default:
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MCE.emitWordBE(getBinaryCodeForInstr(*I));
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break;
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case PPC::IMPLICIT_DEF_GPR:
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case PPC::IMPLICIT_DEF_GPRC:
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case PPC::IMPLICIT_DEF_G8RC:
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case PPC::IMPLICIT_DEF_F8:
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case PPC::IMPLICIT_DEF_F4:
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case PPC::IMPLICIT_DEF_VRRC:
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@ -58,6 +58,8 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
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// PowerPC has no SREM/UREM instructions
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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// We don't support sin/cos/sqrt/fmod
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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@ -53,6 +53,14 @@ def HI48_64 : SDNodeXForm<imm, [{
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}]>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions.
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//
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def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; $rD = IMPLICIT_DEF_G8RC",
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[(set G8RC:$rD, (undef))]>;
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//===----------------------------------------------------------------------===//
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// Fixed point instructions.
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//
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@ -134,7 +142,12 @@ def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
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"addis $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
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def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
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"subfic $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
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def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"subf $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
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def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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@ -326,9 +339,9 @@ def : Pat<(i32 (trunc G8RC:$in)),
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(OR8To4 G8RC:$in, G8RC:$in)>;
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// SHL/SRL
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def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
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def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
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(RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
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def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
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def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
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(RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
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// Hi and Lo for Darwin Global Addresses.
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@ -252,7 +252,7 @@ def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
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def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
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"UPDATE_VRSAVE $rD, $rS", []>;
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}
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def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
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def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
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[(set GPRC:$rD, (undef))]>;
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def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
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[(set F8RC:$rD, (undef))]>;
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