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Change the names of functions isMips* to hasMips*.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140214 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-09-20 23:53:09 +00:00
parent 4d1d86bac9
commit 5663344127
4 changed files with 15 additions and 15 deletions
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2
lib/Target/Mips/MipsISelDAGToDAG.cpp
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@ -262,7 +262,7 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
/// Special Muls /// Special Muls
case ISD::MUL: case ISD::MUL:
if (Subtarget.isMips32()) if (Subtarget.hasMips32())
break; break;
case ISD::MULHS: case ISD::MULHS:
case ISD::MULHU: { case ISD::MULHU: {

10
lib/Target/Mips/MipsISelLowering.cpp
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@ -143,7 +143,7 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::CTTZ, MVT::i32, Expand); setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::ROTL, MVT::i32, Expand); setOperationAction(ISD::ROTL, MVT::i32, Expand);
if (!Subtarget->isMips32r2()) if (!Subtarget->hasMips32r2())
setOperationAction(ISD::ROTR, MVT::i32, Expand); setOperationAction(ISD::ROTR, MVT::i32, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
@ -378,7 +378,7 @@ static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
if (DCI.isBeforeLegalize()) if (DCI.isBeforeLegalize())
return SDValue(); return SDValue();
if (Subtarget->isMips32() && SelectMadd(N, &DAG)) if (Subtarget->hasMips32() && SelectMadd(N, &DAG))
return SDValue(N, 0); return SDValue(N, 0);
return SDValue(); return SDValue();
@ -390,7 +390,7 @@ static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
if (DCI.isBeforeLegalize()) if (DCI.isBeforeLegalize())
return SDValue(); return SDValue();
if (Subtarget->isMips32() && SelectMsub(N, &DAG)) if (Subtarget->hasMips32() && SelectMsub(N, &DAG))
return SDValue(N, 0); return SDValue(N, 0);
return SDValue(); return SDValue();
@ -526,7 +526,7 @@ static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
// Pattern match EXT. // Pattern match EXT.
// $dst = and ((sra or srl) $src , pos), (2**size - 1) // $dst = and ((sra or srl) $src , pos), (2**size - 1)
// => ext $dst, $src, size, pos // => ext $dst, $src, size, pos
if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2()) if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
return SDValue(); return SDValue();
SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
@ -567,7 +567,7 @@ static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
// where mask1 = (2**size - 1) << pos, mask0 = ~mask1 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
// => ins $dst, $src, size, pos, $src1 // => ins $dst, $src, size, pos, $src1
if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2()) if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
return SDValue(); return SDValue();
SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);

10
lib/Target/Mips/MipsInstrInfo.td
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@ -125,8 +125,8 @@ def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
def HasBitCount : Predicate<"Subtarget.hasBitCount()">; def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
def HasSwap : Predicate<"Subtarget.hasSwap()">; def HasSwap : Predicate<"Subtarget.hasSwap()">;
def HasCondMov : Predicate<"Subtarget.hasCondMov()">; def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
def IsMips32 : Predicate<"Subtarget.isMips32()">; def HasMips32 : Predicate<"Subtarget.hasMips32()">;
def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">; def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions. // Mips Operand, Complex Patterns and Transformations Definitions.
@ -409,7 +409,7 @@ class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src),
class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins, class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins,
list<dag> pattern, InstrItinClass itin>: list<dag> pattern, InstrItinClass itin>:
FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
pattern, itin>, Requires<[IsMips32r2]> { pattern, itin>, Requires<[HasMips32r2]> {
bits<5> pos; bits<5> pos;
bits<5> sz; bits<5> sz;
let rd = sz; let rd = sz;
@ -546,7 +546,7 @@ def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>; def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
// Rotate Instructions // Rotate Instructions
let Predicates = [IsMips32r2] in { let Predicates = [HasMips32r2] in {
def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>; def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>; def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
} }
@ -683,7 +683,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>;
// MUL is a assembly macro in the current used ISAs. In recent ISA's // MUL is a assembly macro in the current used ISAs. In recent ISA's
// it is a real instruction. // it is a real instruction.
def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>; def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[HasMips32]>;
def RDHWR : ReadHardware; def RDHWR : ReadHardware;

8
lib/Target/Mips/MipsSubtarget.h
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@ -105,11 +105,11 @@ public:
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS); void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool isMips32() const { return MipsArchVersion >= Mips32; } bool hasMips32() const { return MipsArchVersion >= Mips32; }
bool isMips32r2() const { return MipsArchVersion == Mips32r2 || bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
MipsArchVersion == Mips64r2; } MipsArchVersion == Mips64r2; }
bool isMips64() const { return MipsArchVersion >= Mips64; } bool hassMips64() const { return MipsArchVersion >= Mips64; }
bool isMips64r2() const { return MipsArchVersion == Mips64r2; } bool hassMips64r2() const { return MipsArchVersion == Mips64r2; }
bool isLittle() const { return IsLittle; } bool isLittle() const { return IsLittle; }
bool isFP64bit() const { return IsFP64bit; } bool isFP64bit() const { return IsFP64bit; }