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https://github.com/c64scene-ar/llvm-6502.git
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Missed pieces for ARM HardFP ABI.
Patch by Sandeep Patel! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78225 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
ab90b28adc
commit
567d14f07c
@ -111,6 +111,7 @@ def CC_ARM_AAPCS_VFP : CallingConv<[
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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@ -122,6 +123,7 @@ def RetCC_ARM_AAPCS_VFP : CallingConv<[
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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@ -662,7 +662,8 @@ static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
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/// given CallingConvention value.
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CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
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bool Return) const {
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bool Return,
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bool isVarArg) const {
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switch (CC) {
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default:
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llvm_unreachable("Unsupported calling convention");
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@ -671,7 +672,7 @@ CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
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// Use target triple & subtarget features to do actual dispatch.
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if (Subtarget->isAAPCS_ABI()) {
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if (Subtarget->hasVFP2() &&
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FloatABIType == FloatABI::Hard)
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FloatABIType == FloatABI::Hard && !isVarArg)
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return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
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else
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return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
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@ -700,7 +701,8 @@ ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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RVLocs, *DAG.getContext());
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CCInfo.AnalyzeCallResult(Ins,
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CCAssignFnForNode(CallConv, /* Return*/ true));
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CCAssignFnForNode(CallConv, /* Return*/ true,
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isVarArg));
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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@ -832,7 +834,8 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
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*DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs,
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CCAssignFnForNode(CallConv, /* Return*/ false));
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CCAssignFnForNode(CallConv, /* Return*/ false,
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isVarArg));
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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@ -873,7 +876,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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break;
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}
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// f64 and v2f64 are passed in i32 pairs and must be split into pieces
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// f64 and v2f64 might be passed in i32 pairs and must be split into pieces
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if (VA.needsCustom()) {
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if (VA.getLocVT() == MVT::v2f64) {
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SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
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@ -1034,7 +1037,8 @@ ARMTargetLowering::LowerReturn(SDValue Chain,
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*DAG.getContext());
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// Analyze outgoing return values.
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CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true));
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CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
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isVarArg));
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// If this is the first return lowered for this function, add
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// the regs to the liveout set for the function.
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@ -1422,7 +1426,8 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
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*DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins,
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CCAssignFnForNode(CallConv, /* Return*/ false));
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CCAssignFnForNode(CallConv, /* Return*/ false,
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isVarArg));
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SmallVector<SDValue, 16> ArgValues;
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@ -1455,18 +1460,23 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
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} else {
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TargetRegisterClass *RC;
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if (FloatABIType == FloatABI::Hard && RegVT == MVT::f32)
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bool IsHardFloatCC = (CallConv == CallingConv::ARM_AAPCS_VFP);
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if (IsHardFloatCC && RegVT == MVT::f32)
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RC = ARM::SPRRegisterClass;
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else if (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)
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else if (IsHardFloatCC && RegVT == MVT::f64)
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RC = ARM::DPRRegisterClass;
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else if (IsHardFloatCC && RegVT == MVT::v2f64)
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RC = ARM::QPRRegisterClass;
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else if (AFI->isThumb1OnlyFunction())
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RC = ARM::tGPRRegisterClass;
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else
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RC = ARM::GPRRegisterClass;
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assert((RegVT == MVT::i32 || RegVT == MVT::f32 ||
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(FloatABIType == FloatABI::Hard && RegVT == MVT::f64)) &&
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"RegVT not supported by formal arguments Lowering");
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(IsHardFloatCC &&
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((RegVT == MVT::f64) || (RegVT == MVT::v2f64)))) &&
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"RegVT not supported by FORMAL_ARGUMENTS Lowering");
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// Transform the arguments in physical registers into virtual ones.
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unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
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@ -235,7 +235,7 @@ namespace llvm {
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SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
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CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return) const;
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CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return, bool isVarArg) const;
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SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
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DebugLoc dl, SelectionDAG &DAG,
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const CCValAssign &VA,
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@ -1108,6 +1108,11 @@ bool ARMAsmPrinter::doInitialization(Module &M) {
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O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
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<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
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// Hard float. Use both S and D registers and conform to AAPCS-VFP.
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if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
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O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
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<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
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// FIXME: Should we signal R9 usage?
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}
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13
test/CodeGen/ARM/hardfloat_neon.ll
Normal file
13
test/CodeGen/ARM/hardfloat_neon.ll
Normal file
@ -0,0 +1,13 @@
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; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi -mattr=+neon -float-abi=hard
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define <16 x i8> @vmulQi8_reg(<16 x i8> %A, <16 x i8> %B) nounwind {
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%tmp1 = mul <16 x i8> %A, %B
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ret <16 x i8> %tmp1
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}
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define <16 x i8> @f(<16 x i8> %a, <16 x i8> %b) {
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%tmp = call <16 x i8> @g(<16 x i8> %b)
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ret <16 x i8> %tmp
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}
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declare <16 x i8> @g(<16 x i8>)
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