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Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171461 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -266,7 +266,7 @@ def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
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// unsigned division/remainder
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let hasSideEffects = 0 in {
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let hasSideEffects = 1 in { // so that we don't speculatively execute
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let Defs = [AL,EFLAGS,AX], Uses = [AX] in
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def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
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"div{b}\t$src", [], IIC_DIV8_REG>;
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@ -142,3 +142,35 @@ save_state_and_return:
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}
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declare void @BZ2_bz__AssertH__fail()
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; Make sure we don't speculate on div/idiv instructions
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; CHECK: test_idiv
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; CHECK-NOT: cmov
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define i32 @test_idiv(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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%1 = icmp eq i32 %b, 0
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br i1 %1, label %4, label %2
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; <label>:2 ; preds = %0
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%3 = sdiv i32 %a, %b
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br label %4
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; <label>:4 ; preds = %0, %2
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%5 = phi i32 [ %3, %2 ], [ %a, %0 ]
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ret i32 %5
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}
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; CHECK: test_div
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; CHECK-NOT: cmov
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define i32 @test_div(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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%1 = icmp eq i32 %b, 0
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br i1 %1, label %4, label %2
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; <label>:2 ; preds = %0
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%3 = udiv i32 %a, %b
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br label %4
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; <label>:4 ; preds = %0, %2
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%5 = phi i32 [ %3, %2 ], [ %a, %0 ]
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ret i32 %5
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}
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