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ARM STRH encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -202,6 +202,8 @@ namespace {
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Binary |= (Reg << 13);
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return Binary;
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}
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uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
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{ return 0; }
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uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
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// {12-9} = reg
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// {8} = (U)nsigned (add == '1', sub == '0')
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@ -735,14 +735,19 @@ class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 0; // S bit
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let Inst{7} = 1;
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{24} = 1; // P bit
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bits<14> addr;
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bits<4> Rt;
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let Inst{27-25} = 0b000;
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let Inst{24} = 1; // P bit
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let Inst{23} = addr{8}; // U bit
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let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
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let Inst{21} = 0; // W bit
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let Inst{20} = 0; // L bit
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let Inst{19-16} = addr{12-9}; // Rn
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let Inst{15-12} = Rt; // Rt
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{7-4} = 0b1011;
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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}
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class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
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string asm, list<dag> pattern>
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@ -442,6 +442,7 @@ def am2offset : Operand<i32>,
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//
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def addrmode3 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectAddrMode3", []> {
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string EncoderMethod = "getAddrMode3OpValue";
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let PrintMethod = "printAddrMode3Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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@ -1604,9 +1605,9 @@ def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
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// Store
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// Stores with truncate
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def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
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IIC_iStore_bh_r, "strh", "\t$src, $addr",
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[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
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def STRH : AI3sth<(outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
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IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
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[(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
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// Store doubleword
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
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@ -94,6 +94,9 @@ public:
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case ARM_AM::ib: return 3;
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}
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}
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/// getAddrMode3OpValue - Return encoding for addrmode3 operands.
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uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
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uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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@ -306,7 +309,7 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
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// {4} = 0
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// {6-5} = type
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// {11-7} = imm
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int64_t Binary = Rm;
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uint32_t Binary = Rm;
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Binary |= Rn << 13;
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Binary |= SBits << 5;
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Binary |= ShImm << 7;
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@ -315,6 +318,28 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
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return Binary;
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}
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uint32_t ARMMCCodeEmitter::
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getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// {13} 1 == imm8, 0 == Rm
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// {12-9} Rn
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// {8} isAdd
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// {7-4} imm7_4/zero
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// {3-0} imm3_0/Rm
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const MCOperand &MO = MI.getOperand(OpIdx);
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const MCOperand &MO1 = MI.getOperand(OpIdx+1);
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const MCOperand &MO2 = MI.getOperand(OpIdx+2);
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unsigned Rn = getARMRegisterNumbering(MO.getReg());
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unsigned Imm = MO2.getImm();
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bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
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bool isImm = MO1.getReg() == 0;
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uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
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// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
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if (!isImm)
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Imm8 = getARMRegisterNumbering(MO1.getReg());
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return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
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}
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/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
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uint32_t ARMMCCodeEmitter::
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getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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