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ARM STRH encoding information.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-11 01:09:40 +00:00
parent f00833c401
commit 570a922691
4 changed files with 44 additions and 11 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -202,6 +202,8 @@ namespace {
Binary |= (Reg << 13);
return Binary;
}
uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
{ return 0; }
uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
// {12-9} = reg
// {8} = (U)nsigned (add == '1', sub == '0')

19
lib/Target/ARM/ARMInstrFormats.td
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@ -735,14 +735,19 @@ class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 0; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1011;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>

7
lib/Target/ARM/ARMInstrInfo.td
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@ -442,6 +442,7 @@ def am2offset : Operand<i32>,
//
def addrmode3 : Operand<i32>,
ComplexPattern<i32, 3, "SelectAddrMode3", []> {
string EncoderMethod = "getAddrMode3OpValue";
let PrintMethod = "printAddrMode3Operand";
let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
}
@ -1604,9 +1605,9 @@ def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
// Store
// Stores with truncate
def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
IIC_iStore_bh_r, "strh", "\t$src, $addr",
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
def STRH : AI3sth<(outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
[(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
// Store doubleword
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,

27
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -94,6 +94,9 @@ public:
case ARM_AM::ib: return 3;
}
}
/// getAddrMode3OpValue - Return encoding for addrmode3 operands.
uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
@ -306,7 +309,7 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
// {4} = 0
// {6-5} = type
// {11-7} = imm
int64_t Binary = Rm;
uint32_t Binary = Rm;
Binary |= Rn << 13;
Binary |= SBits << 5;
Binary |= ShImm << 7;
@ -315,6 +318,28 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
return Binary;
}
uint32_t ARMMCCodeEmitter::
getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
// {13} 1 == imm8, 0 == Rm
// {12-9} Rn
// {8} isAdd
// {7-4} imm7_4/zero
// {3-0} imm3_0/Rm
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
const MCOperand &MO2 = MI.getOperand(OpIdx+2);
unsigned Rn = getARMRegisterNumbering(MO.getReg());
unsigned Imm = MO2.getImm();
bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
bool isImm = MO1.getReg() == 0;
uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
if (!isImm)
Imm8 = getARMRegisterNumbering(MO1.getReg());
return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
}
/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
uint32_t ARMMCCodeEmitter::
getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,