Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInstrInfo.cpp

@@ -636,7 +636,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   if (I != MBB.end()) DL = I->getDebugLoc();
 
   if (RC == ARM::GPRRegisterClass) {
-    AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::STRrr)))
+    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
                    .addReg(SrcReg, getKillRegState(isKill))
                    .addFrameIndex(FI).addReg(0).addImm(0));
   } else if (RC == ARM::DPRRegisterClass) {
@@ -659,7 +659,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   if (I != MBB.end()) DL = I->getDebugLoc();
 
   if (RC == ARM::GPRRegisterClass) {
-    AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::LDRrr)), DestReg)
+    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
                    .addFrameIndex(FI).addReg(0).addImm(0));
   } else if (RC == ARM::DPRRegisterClass) {
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
@@ -679,7 +679,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
   unsigned OpNum = Ops[0];
   unsigned Opc = MI->getOpcode();
   MachineInstr *NewMI = NULL;
-  if (Opc == getOpcode(ARMII::MOVr)) {
+  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
     // If it is updating CPSR, then it cannot be folded.
     if (MI->getOperand(4).getReg() != ARM::CPSR) {
       unsigned Pred = MI->getOperand(2).getImm();
@@ -688,19 +688,32 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
         unsigned SrcReg = MI->getOperand(1).getReg();
         bool isKill = MI->getOperand(1).isKill();
         bool isUndef = MI->getOperand(1).isUndef();
-        NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::STRrr)))
+        if (Opc == ARM::MOVr)
-          .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+          NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
-          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
+            .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+            .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
+        else // ARM::t2MOVr
+          NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
+            .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+            .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
       } else {          // move -> load
         unsigned DstReg = MI->getOperand(0).getReg();
         bool isDead = MI->getOperand(0).isDead();
         bool isUndef = MI->getOperand(0).isUndef();
-        NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::LDRrr)))
+        if (Opc == ARM::MOVr)
-          .addReg(DstReg,
+          NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
-                  RegState::Define |
+            .addReg(DstReg,
-                  getDeadRegState(isDead) |
+                    RegState::Define |
-                  getUndefRegState(isUndef))
+                    getDeadRegState(isDead) |
-          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
+                    getUndefRegState(isUndef))
+            .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
+        else // ARM::t2MOVr
+          NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
+            .addReg(DstReg,
+                    RegState::Define |
+                    getDeadRegState(isDead) |
+                    getUndefRegState(isUndef))
+            .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
       }
     }
   }
@@ -767,7 +780,7 @@ ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
   if (Ops.size() != 1) return false;
 
   unsigned Opc = MI->getOpcode();
-  if (Opc == getOpcode(ARMII::MOVr)) {
+  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
     // If it is updating CPSR, then it cannot be folded.
     return MI->getOperand(4).getReg() != ARM::CPSR;
   } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {

lib/Target/ARM/ARMBaseInstrInfo.h

@@ -168,10 +168,8 @@ namespace ARMII {
     B,
     Bcc,
     BX_RET,
-    LDRrr,
     LDRri,
     MOVr,
-    STRrr,
     STRri,
     SUBri,
     SUBrs,
@@ -271,6 +269,7 @@ public:
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,
                             const TargetRegisterClass *SrcRC) const;
+
   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MBBI,
                                    unsigned SrcReg, bool isKill, int FrameIndex,

lib/Target/ARM/ARMBaseRegisterInfo.cpp

@@ -1305,8 +1305,7 @@ emitPrologue(MachineFunction &MF) const {
 
   // Build the new SUBri to adjust SP for integer callee-save spill area 1.
   emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
-  movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STRrr),
+  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
-                         getOpcode(ARMII::STRri), 1, STI);
 
   // Darwin ABI requires FP to point to the stack slot that contains the
   // previous FP.
@@ -1321,8 +1320,7 @@ emitPrologue(MachineFunction &MF) const {
   emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
 
   // Build the new SUBri to adjust SP for FP callee-save spill area.
-  movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STRrr),
+  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
-                         getOpcode(ARMII::STRri), 2, STI);
   emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
 
   // Determine starting offsets of spill areas.
@@ -1362,8 +1360,8 @@ static bool isCSRestore(MachineInstr *MI,
                         const ARMBaseInstrInfo &TII, 
                         const unsigned *CSRegs) {
   return ((MI->getOpcode() == (int)ARM::FLDD ||
-           MI->getOpcode() == (int)TII.getOpcode(ARMII::LDRrr) ||
+           MI->getOpcode() == (int)ARM::LDR ||
-           MI->getOpcode() == (int)TII.getOpcode(ARMII::LDRri)) &&
+           MI->getOpcode() == (int)ARM::t2LDRi12) &&
           MI->getOperand(1).isFI() &&
           isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
 }
@@ -1428,13 +1426,11 @@ emitEpilogue(MachineFunction &MF,
     emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
 
     // Move SP to start of integer callee save spill area 1.
-    movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDRrr),
+    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
-                           getOpcode(ARMII::LDRri), 2, STI);
     emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
 
     // Move SP to SP upon entry to the function.
-    movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDRrr),
+    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
-                           getOpcode(ARMII::LDRri), 1, STI);
     emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
   }
 

lib/Target/ARM/ARMInstrInfo.cpp

@@ -71,10 +71,8 @@ getOpcode(ARMII::Op Op) const {
   case ARMII::B: return ARM::B;
   case ARMII::Bcc: return ARM::Bcc;
   case ARMII::BX_RET: return ARM::BX_RET;
-  case ARMII::LDRrr: return ARM::LDR;
   case ARMII::LDRri: return 0;
   case ARMII::MOVr: return ARM::MOVr;
-  case ARMII::STRrr: return ARM::STR;
   case ARMII::STRri: return 0;
   case ARMII::SUBri: return ARM::SUBri;
   case ARMII::SUBrs: return ARM::SUBrs;

lib/Target/ARM/Thumb1InstrInfo.cpp

@@ -38,10 +38,8 @@ unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
   case ARMII::B: return ARM::tB;
   case ARMII::Bcc: return ARM::tBcc;
   case ARMII::BX_RET: return ARM::tBX_RET;
-  case ARMII::LDRrr: return ARM::tLDR;
   case ARMII::LDRri: return 0;
   case ARMII::MOVr: return ARM::tMOVr;
-  case ARMII::STRrr: return ARM::tSTR;
   case ARMII::STRri: return 0;
   case ARMII::SUBri: return ARM::tSUBi8;
   case ARMII::SUBrs: return 0;

lib/Target/ARM/Thumb2InstrInfo.cpp

@@ -39,10 +39,8 @@ unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
   case ARMII::B: return ARM::t2B;
   case ARMII::Bcc: return ARM::t2Bcc;
   case ARMII::BX_RET: return ARM::tBX_RET;
-  case ARMII::LDRrr: return ARM::t2LDRs;
   case ARMII::LDRri: return ARM::t2LDRi12;
   case ARMII::MOVr: return ARM::t2MOVr;
-  case ARMII::STRrr: return ARM::t2STRs;
   case ARMII::STRri: return ARM::t2STRi12;
   case ARMII::SUBri: return ARM::t2SUBri;
   case ARMII::SUBrs: return ARM::t2SUBrs;
@@ -102,3 +100,36 @@ Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
   // Handle SPR, DPR, and QPR copies.
   return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
 }
+
+void Thumb2InstrInfo::
+storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+                    unsigned SrcReg, bool isKill, int FI,
+                    const TargetRegisterClass *RC) const {
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (I != MBB.end()) DL = I->getDebugLoc();
+
+  if (RC == ARM::GPRRegisterClass) {
+    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
+                   .addReg(SrcReg, getKillRegState(isKill))
+                   .addFrameIndex(FI).addImm(0));
+    return;
+  }
+
+  ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
+}
+
+void Thumb2InstrInfo::
+loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+                     unsigned DestReg, int FI,
+                     const TargetRegisterClass *RC) const {
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (I != MBB.end()) DL = I->getDebugLoc();
+
+  if (RC == ARM::GPRRegisterClass) {
+    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
+                   .addFrameIndex(FI).addImm(0));
+    return;
+  }
+
+  ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);
+}

lib/Target/ARM/Thumb2InstrInfo.h

@@ -43,6 +43,16 @@ public:
                     const TargetRegisterClass *DestRC,
                     const TargetRegisterClass *SrcRC) const;
 
+  void storeRegToStackSlot(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MBBI,
+                           unsigned SrcReg, bool isKill, int FrameIndex,
+                           const TargetRegisterClass *RC) const;
+
+  void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MBBI,
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC) const;
+
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).