mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Masked load and store codegen - fixed 128-bit vectors
The codegen failed on 128-bit types on AVX2. I added patterns and in td files and tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224647 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
7fc3bdab6a
commit
573b762b68
@ -1314,23 +1314,19 @@ void X86TargetLowering::resetOperationActions() {
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i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
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MVT VT = (MVT::SimpleValueType)i;
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if (VT.getScalarSizeInBits() >= 32) {
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setOperationAction(ISD::MLOAD, VT, Legal);
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setOperationAction(ISD::MSTORE, VT, Legal);
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}
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// Extract subvector is special because the value type
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// (result) is 128-bit but the source is 256-bit wide.
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if (VT.is128BitVector()) {
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if (VT.getScalarSizeInBits() >= 32) {
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setOperationAction(ISD::MLOAD, VT, Custom);
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setOperationAction(ISD::MSTORE, VT, Custom);
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}
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
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}
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// Do not attempt to custom lower other non-256-bit vectors
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if (!VT.is256BitVector())
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continue;
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if (VT.getScalarSizeInBits() >= 32) {
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setOperationAction(ISD::MLOAD, VT, Legal);
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setOperationAction(ISD::MSTORE, VT, Legal);
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}
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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@ -1499,10 +1495,6 @@ void X86TargetLowering::resetOperationActions() {
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// (result) is 256/128-bit but the source is 512-bit wide.
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if (VT.is128BitVector() || VT.is256BitVector()) {
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
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if ( EltSize >= 32) {
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setOperationAction(ISD::MLOAD, VT, Legal);
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setOperationAction(ISD::MSTORE, VT, Legal);
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}
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}
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if (VT.getVectorElementType() == MVT::i1)
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
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@ -2211,6 +2211,11 @@ def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
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def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
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(VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
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def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
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(v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
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(INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
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(v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
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defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
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"16", "8", "4", SSEPackedInt, HasAVX512>,
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avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
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@ -8966,20 +8966,26 @@ defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
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int_x86_avx2_maskstore_q_256>, VEX_W;
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def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
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(VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
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(VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
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def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
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(VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
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def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
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(VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
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def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
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(VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
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def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
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(VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
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(VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
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def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
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(bc_v8f32 (v8i32 immAllZerosV)))),
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(VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
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(VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
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def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
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(VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
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(VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
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VR256:$mask)>;
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def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
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@ -8992,21 +8998,42 @@ def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0)
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(VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
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VR256:$mask)>;
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def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
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(VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
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def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
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(bc_v4f32 (v4i32 immAllZerosV)))),
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(VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
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def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
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(VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
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VR128:$mask)>;
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def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
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(VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
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def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
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(VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
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def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
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(VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
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VR128:$mask)>;
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def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
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(VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
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(VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
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def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
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(VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
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def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
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(VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
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(VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
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def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
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(v4f64 immAllZerosV))),
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(VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
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(VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
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def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
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(VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
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(VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
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VR256:$mask)>;
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def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
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@ -9020,6 +9047,33 @@ def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0)
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(VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
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VR256:$mask)>;
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def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
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(VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
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def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
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(VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
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def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
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(VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
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def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
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(v2f64 immAllZerosV))),
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(VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
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def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
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(VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
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VR128:$mask)>;
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def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
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(VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
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def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
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(bc_v2i64 (v4i32 immAllZerosV)))),
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(VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
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def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
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(VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
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VR128:$mask)>;
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//===----------------------------------------------------------------------===//
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// Variable Bit Shifts
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@ -41,8 +41,8 @@ define void @test3(<16 x i32> %trigger, i8* %addr, <16 x i32> %val) {
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; AVX512: vmovups (%rdi), %zmm{{.*{%k[1-7]}}}
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; AVX2-LABEL: test4
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; AVX2: vpmaskmovd {{.*}}(%rdi)
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; AVX2: vpmaskmovd {{.*}}(%rdi)
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; AVX2: vmaskmovps {{.*}}(%rdi)
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; AVX2: vmaskmovps {{.*}}(%rdi)
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; AVX2: blend
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define <16 x float> @test4(<16 x i32> %trigger, i8* %addr, <16 x float> %dst) {
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%mask = icmp eq <16 x i32> %trigger, zeroinitializer
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@ -54,9 +54,9 @@ define <16 x float> @test4(<16 x i32> %trigger, i8* %addr, <16 x float> %dst) {
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; AVX512: vmovupd (%rdi), %zmm1 {%k1}
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; AVX2-LABEL: test5
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; AVX2: vpmaskmovq
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; AVX2: vmaskmovpd
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; AVX2: vblendvpd
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; AVX2: vpmaskmovq
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; AVX2: vmaskmovpd
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; AVX2: vblendvpd
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define <8 x double> @test5(<8 x i32> %trigger, i8* %addr, <8 x double> %dst) {
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%mask = icmp eq <8 x i32> %trigger, zeroinitializer
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@ -64,10 +64,80 @@ define <8 x double> @test5(<8 x i32> %trigger, i8* %addr, <8 x double> %dst) {
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ret <8 x double> %res
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}
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declare <16 x i32> @llvm.masked.load.v16i32(i8*, <16 x i32>, i32, <16 x i1>)
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declare void @llvm.masked.store.v16i32(i8*, <16 x i32>, i32, <16 x i1>)
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declare <16 x float> @llvm.masked.load.v16f32(i8*, <16 x float>, i32, <16 x i1>)
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declare void @llvm.masked.store.v16f32(i8*, <16 x float>, i32, <16 x i1>)
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declare <8 x double> @llvm.masked.load.v8f64(i8*, <8 x double>, i32, <8 x i1>)
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declare void @llvm.masked.store.v8f64(i8*, <8 x double>, i32, <8 x i1>)
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; AVX2-LABEL: test6
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; AVX2: vmaskmovpd
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; AVX2: vblendvpd
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define <2 x double> @test6(<2 x i64> %trigger, i8* %addr, <2 x double> %dst) {
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%mask = icmp eq <2 x i64> %trigger, zeroinitializer
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%res = call <2 x double> @llvm.masked.load.v2f64(i8* %addr, <2 x double>%dst, i32 4, <2 x i1>%mask)
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ret <2 x double> %res
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}
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; AVX2-LABEL: test7
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; AVX2: vmaskmovps {{.*}}(%rdi)
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; AVX2: blend
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define <4 x float> @test7(<4 x i32> %trigger, i8* %addr, <4 x float> %dst) {
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%mask = icmp eq <4 x i32> %trigger, zeroinitializer
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%res = call <4 x float> @llvm.masked.load.v4f32(i8* %addr, <4 x float>%dst, i32 4, <4 x i1>%mask)
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ret <4 x float> %res
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}
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; AVX2-LABEL: test8
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; AVX2: vpmaskmovd {{.*}}(%rdi)
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; AVX2: blend
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define <4 x i32> @test8(<4 x i32> %trigger, i8* %addr, <4 x i32> %dst) {
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%mask = icmp eq <4 x i32> %trigger, zeroinitializer
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%res = call <4 x i32> @llvm.masked.load.v4i32(i8* %addr, <4 x i32>%dst, i32 4, <4 x i1>%mask)
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ret <4 x i32> %res
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}
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; AVX2-LABEL: test9
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; AVX2: vpmaskmovd %xmm
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define void @test9(<4 x i32> %trigger, i8* %addr, <4 x i32> %val) {
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%mask = icmp eq <4 x i32> %trigger, zeroinitializer
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call void @llvm.masked.store.v4i32(i8* %addr, <4 x i32>%val, i32 4, <4 x i1>%mask)
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ret void
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}
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; AVX2-LABEL: test10
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; AVX2: vmaskmovpd (%rdi), %ymm
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; AVX2: blend
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define <4 x double> @test10(<4 x i32> %trigger, i8* %addr, <4 x double> %dst) {
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%mask = icmp eq <4 x i32> %trigger, zeroinitializer
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%res = call <4 x double> @llvm.masked.load.v4f64(i8* %addr, <4 x double>%dst, i32 4, <4 x i1>%mask)
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ret <4 x double> %res
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}
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; AVX2-LABEL: test11
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; AVX2: vmaskmovps
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; AVX2: vblendvps
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define <8 x float> @test11(<8 x i32> %trigger, i8* %addr, <8 x float> %dst) {
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%mask = icmp eq <8 x i32> %trigger, zeroinitializer
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%res = call <8 x float> @llvm.masked.load.v8f32(i8* %addr, <8 x float>%dst, i32 4, <8 x i1>%mask)
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ret <8 x float> %res
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}
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; AVX2-LABEL: test12
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; AVX2: vpmaskmovd %ymm
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define void @test12(<8 x i32> %trigger, i8* %addr, <8 x i32> %val) {
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%mask = icmp eq <8 x i32> %trigger, zeroinitializer
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call void @llvm.masked.store.v8i32(i8* %addr, <8 x i32>%val, i32 4, <8 x i1>%mask)
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ret void
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}
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declare <16 x i32> @llvm.masked.load.v16i32(i8*, <16 x i32>, i32, <16 x i1>)
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declare <4 x i32> @llvm.masked.load.v4i32(i8*, <4 x i32>, i32, <4 x i1>)
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declare void @llvm.masked.store.v16i32(i8*, <16 x i32>, i32, <16 x i1>)
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declare void @llvm.masked.store.v8i32(i8*, <8 x i32>, i32, <8 x i1>)
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declare void @llvm.masked.store.v4i32(i8*, <4 x i32>, i32, <4 x i1>)
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declare <16 x float> @llvm.masked.load.v16f32(i8*, <16 x float>, i32, <16 x i1>)
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declare <8 x float> @llvm.masked.load.v8f32(i8*, <8 x float>, i32, <8 x i1>)
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declare <4 x float> @llvm.masked.load.v4f32(i8*, <4 x float>, i32, <4 x i1>)
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declare void @llvm.masked.store.v16f32(i8*, <16 x float>, i32, <16 x i1>)
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declare <8 x double> @llvm.masked.load.v8f64(i8*, <8 x double>, i32, <8 x i1>)
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declare <4 x double> @llvm.masked.load.v4f64(i8*, <4 x double>, i32, <4 x i1>)
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declare <2 x double> @llvm.masked.load.v2f64(i8*, <2 x double>, i32, <2 x i1>)
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declare void @llvm.masked.store.v8f64(i8*, <8 x double>, i32, <8 x i1>)
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declare void @llvm.masked.store.v2f64(i8*, <2 x double>, i32, <2 x i1>)
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declare void @llvm.masked.store.v2i64(i8*, <2 x i64>, i32, <2 x i1>)
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