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[FastISel][AArch64] Don't fold the 'and' instruction into the 'tbz/tbnz' instruction if it is in a different basic block.

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This fixes a bug where the input register was not defined for the 'tbz/tbnz'
instruction. This happened, because we folded the 'and' instruction from a
different basic block.

This fixes rdar://problem/18784013.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220704 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-10-27 19:16:48 +00:00
parent d3a04223e8
commit 5745cad861
2 changed files with 18 additions and 2 deletions
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4
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -2118,7 +2118,7 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
return false;
if (const auto *AI = dyn_cast<BinaryOperator>(LHS))
if (AI->getOpcode() == Instruction::And) {
if (AI->getOpcode() == Instruction::And && isValueAvailable(AI)) {
const Value *AndLHS = AI->getOperand(0);
const Value *AndRHS = AI->getOperand(1);
@ -2165,7 +2165,7 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
bool Is64Bit = BW == 64;
if (TestBit < 32 && TestBit >= 0)
Is64Bit = false;
unsigned Opc = OpcTable[IsBitTest][IsCmpNE][Is64Bit];
const MCInstrDesc &II = TII.get(Opc);

16
test/CodeGen/AArch64/fast-isel-tbz.ll
View File

@ -121,5 +121,21 @@ bb2:
ret i32 0
}
; Test that we don't fold the 'and' instruction into the compare.
define i32 @icmp_eq_and_i32(i32 %a, i1 %c) {
; CHECK-LABEL: icmp_eq_and_i32
; CHECK: and [[REG:w[0-9]+]], w0, #0x4
; CHECK-NEXT: cbz [[REG]], {{LBB.+_3}}
%1 = and i32 %a, 4
br i1 %c, label %bb0, label %bb2
bb0:
%2 = icmp eq i32 %1, 0
br i1 %2, label %bb1, label %bb2, !prof !0
bb1:
ret i32 1
bb2:
ret i32 0
}
!0 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647}
!1 = metadata !{metadata !"branch_weights", i32 2147483647, i32 0}