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[FastISel][AArch64] Don't fold the 'and' instruction into the 'tbz/tbnz' instruction if it is in a different basic block.
This fixes a bug where the input register was not defined for the 'tbz/tbnz' instruction. This happened, because we folded the 'and' instruction from a different basic block. This fixes rdar://problem/18784013. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220704 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2118,7 +2118,7 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
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return false;
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if (const auto *AI = dyn_cast<BinaryOperator>(LHS))
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if (AI->getOpcode() == Instruction::And) {
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if (AI->getOpcode() == Instruction::And && isValueAvailable(AI)) {
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const Value *AndLHS = AI->getOperand(0);
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const Value *AndRHS = AI->getOperand(1);
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@ -2165,7 +2165,7 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
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bool Is64Bit = BW == 64;
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if (TestBit < 32 && TestBit >= 0)
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Is64Bit = false;
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unsigned Opc = OpcTable[IsBitTest][IsCmpNE][Is64Bit];
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const MCInstrDesc &II = TII.get(Opc);
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@ -121,5 +121,21 @@ bb2:
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ret i32 0
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}
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; Test that we don't fold the 'and' instruction into the compare.
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define i32 @icmp_eq_and_i32(i32 %a, i1 %c) {
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; CHECK-LABEL: icmp_eq_and_i32
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; CHECK: and [[REG:w[0-9]+]], w0, #0x4
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; CHECK-NEXT: cbz [[REG]], {{LBB.+_3}}
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%1 = and i32 %a, 4
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br i1 %c, label %bb0, label %bb2
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bb0:
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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!0 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647}
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!1 = metadata !{metadata !"branch_weights", i32 2147483647, i32 0}
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