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Remove the use of the subtarget in MCCodeEmitter creation and

Browse Source 
update all ports accordingly. Required a couple of small rewrites
in handling subtarget features during creation in PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231861 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-03-10 22:03:14 +00:00
parent f3d745cdc9
commit 57849e3bb4
26 changed files with 29 additions and 67 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
include/llvm/Support/TargetRegistry.h
View File

@ -125,7 +125,6 @@ namespace llvm {
const MCSubtargetInfo &STI);
typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
typedef MCStreamer *(*MCObjectStreamerCtorTy)(
const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &TAB,
@ -406,11 +405,10 @@ namespace llvm {
/// createMCCodeEmitter - Create a target specific code emitter.
MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) const {
if (!MCCodeEmitterCtorFn)
return nullptr;
return MCCodeEmitterCtorFn(II, MRI, STI, Ctx);
return MCCodeEmitterCtorFn(II, MRI, Ctx);
}
/// createMCObjectStreamer - Create a target specific MCStreamer.
@ -1152,10 +1150,9 @@ namespace llvm {
}
private:
static MCCodeEmitter *Allocator(const MCInstrInfo &/*II*/,
const MCRegisterInfo &/*MRI*/,
const MCSubtargetInfo &/*STI*/,
MCContext &/*Ctx*/) {
static MCCodeEmitter *Allocator(const MCInstrInfo & /*II*/,
const MCRegisterInfo & /*MRI*/,
MCContext & /*Ctx*/) {
return new MCCodeEmitterImpl();
}
};

7
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -176,7 +176,7 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
// Create a code emitter if asked to show the encoding.
MCCodeEmitter *MCE = nullptr;
if (Options.MCOptions.ShowMCEncoding)
MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
TargetCPU);
@ -190,8 +190,7 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
case CGFT_ObjectFile: {
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
*Context);
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
TargetCPU);
if (!MCE || !MAB)
@ -243,7 +242,7 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
const MCRegisterInfo &MRI = *getSubtargetImpl()->getRegisterInfo();
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(
*getSubtargetImpl()->getInstrInfo(), MRI, STI, *Ctx);
*getSubtargetImpl()->getInstrInfo(), MRI, *Ctx);
MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
TargetCPU);
if (!MCE || !MAB)

7
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
View File

@ -38,9 +38,7 @@ class AArch64MCCodeEmitter : public MCCodeEmitter {
AArch64MCCodeEmitter(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT
void operator=(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT
public:
AArch64MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
MCContext &ctx)
: Ctx(ctx) {}
AArch64MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) : Ctx(ctx) {}
~AArch64MCCodeEmitter() {}
@ -205,9 +203,8 @@ public:
MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new AArch64MCCodeEmitter(MCII, STI, Ctx);
return new AArch64MCCodeEmitter(MCII, Ctx);
}
/// getMachineOpValue - Return binary encoding of operand. If the machine

5
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
View File

@ -37,9 +37,8 @@ extern Target TheAArch64beTarget;
extern Target TheARM64Target;
MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCRegisterInfo &MRI, StringRef TT,
StringRef CPU);

2
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -441,14 +441,12 @@ public:
MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new ARMMCCodeEmitter(MCII, Ctx, true);
}
MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new ARMMCCodeEmitter(MCII, Ctx, false);
}

2
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
View File

@ -56,12 +56,10 @@ MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,

10
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
View File

@ -49,9 +49,8 @@ void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {
}
HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
MCSubtargetInfo const &aMST,
MCContext &aMCT)
: MST(aMST), MCT(aMCT), MCII (aMII) {}
: MCT(aMCT), MCII(aMII) {}
void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
@ -75,15 +74,10 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
llvm_unreachable("Only Immediates and Registers implemented right now");
}
MCSubtargetInfo const &HexagonMCCodeEmitter::getSubtargetInfo() const {
return MST;
}
MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
MCRegisterInfo const &MRI,
MCSubtargetInfo const &MST,
MCContext &MCT) {
return new HexagonMCCodeEmitter(MII, MST, MCT);
return new HexagonMCCodeEmitter(MII, MCT);
}
#include "HexagonGenMCCodeEmitter.inc"

4
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h
View File

@ -26,13 +26,11 @@
namespace llvm {
class HexagonMCCodeEmitter : public MCCodeEmitter {
MCSubtargetInfo const &MST;
MCContext &MCT;
MCInstrInfo const &MCII;
public:
HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCSubtargetInfo const &aMST,
MCContext &aMCT);
HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT);
MCSubtargetInfo const &getSubtargetInfo() const;

1
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
View File

@ -34,7 +34,6 @@ MCInstrInfo *createHexagonMCInstrInfo();
MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII,
MCRegisterInfo const &MRI,
MCSubtargetInfo const &MST,
MCContext &MCT);
MCAsmBackend *createHexagonAsmBackend(Target const &T,

2
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -35,14 +35,12 @@
namespace llvm {
MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new MipsMCCodeEmitter(MCII, Ctx, false);
}
MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new MipsMCCodeEmitter(MCII, Ctx, true);
}

2
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
View File

@ -35,11 +35,9 @@ extern Target TheMips64elTarget;
MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCAsmBackend *createMipsAsmBackendEB32(const Target &T,

16
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View File

@ -14,6 +14,7 @@
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCFixupKinds.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
@ -39,10 +40,10 @@ class PPCMCCodeEmitter : public MCCodeEmitter {
bool IsLittleEndian;
public:
PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool isLittle)
: MCII(mcii), CTX(ctx), IsLittleEndian(isLittle) {
}
PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
: MCII(mcii), CTX(ctx),
IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {}
~PPCMCCodeEmitter() {}
unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
@ -158,14 +159,11 @@ public:
};
} // end anonymous namespace
MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
Triple TT(STI.getTargetTriple());
bool IsLittleEndian = TT.getArch() == Triple::ppc64le;
return new PPCMCCodeEmitter(MCII, Ctx, IsLittleEndian);
return new PPCMCCodeEmitter(MCII, Ctx);
}
unsigned PPCMCCodeEmitter::

3
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
View File

@ -34,10 +34,9 @@ class raw_ostream;
extern Target ThePPC32Target;
extern Target ThePPC64Target;
extern Target ThePPC64LETarget;
MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,

1
lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp
View File

@ -17,6 +17,7 @@
#include "InstPrinter/AMDGPUInstPrinter.h"
#include "SIDefines.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"

4
lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h
View File

@ -35,12 +35,10 @@ extern Target TheGCNTarget;
MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCContext &Ctx);
MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,

1
lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
View File

@ -82,7 +82,6 @@ enum FCInstr {
MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new R600MCCodeEmitter(MCII, MRI);
}

1
lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@ -72,7 +72,6 @@ public:
MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new SIMCCodeEmitter(MCII, MRI, Ctx);
}

1
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
View File

@ -74,7 +74,6 @@ public:
MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new SparcMCCodeEmitter(Ctx);
}

1
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
View File

@ -33,7 +33,6 @@ extern Target TheSparcV9Target;
MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCAsmBackend *createSparcAsmBackend(const Target &T,
const MCRegisterInfo &MRI,

1
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
View File

@ -110,7 +110,6 @@ private:
MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &MCSTI,
MCContext &Ctx) {
return new SystemZMCCodeEmitter(MCII, Ctx);
}

1
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
View File

@ -71,7 +71,6 @@ inline unsigned getRegAsGRH32(unsigned Reg) {
MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCAsmBackend *createSystemZMCAsmBackend(const Target &T,

2
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -168,10 +168,8 @@ public:
} // end anonymous namespace
MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new X86MCCodeEmitter(MCII, Ctx);
}

1
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
View File

@ -78,7 +78,6 @@ namespace X86_MC {
MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,

4
lib/Target/X86/X86MCInstLower.cpp
View File

@ -77,8 +77,8 @@ namespace llvm {
X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
MF = &F;
CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
*MF->getSubtarget().getInstrInfo(), *MF->getSubtarget().getRegisterInfo(),
MF->getSubtarget(), MF->getContext()));
*MF->getSubtarget().getInstrInfo(),
*MF->getSubtarget().getRegisterInfo(), MF->getContext()));
}
void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,

2
tools/dsymutil/DwarfLinker.cpp
View File

@ -316,7 +316,7 @@ bool DwarfStreamer::init(Triple TheTriple, StringRef OutputFilename) {
if (!MSTI)
return error("no subtarget info for target " + TripleName, Context);
MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MSTI, *MC);
MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
if (!MCE)
return error("no code emitter for target " + TripleName, Context);

4
tools/llvm-mc/llvm-mc.cpp
View File

@ -457,7 +457,7 @@ int main(int argc, char **argv) {
MCCodeEmitter *CE = nullptr;
MCAsmBackend *MAB = nullptr;
if (ShowEncoding) {
CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
}
Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/ true,
@ -468,7 +468,7 @@ int main(int argc, char **argv) {
Str.reset(TheTarget->createNullStreamer(Ctx));
} else {
assert(FileType == OFT_ObjectFile && "Invalid file type!");
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
Str.reset(TheTarget->createMCObjectStreamer(TripleName, Ctx, *MAB, FOS, CE,
*STI, RelaxAll));