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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -98,23 +98,22 @@ defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub">;
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//===----------------------------------------------------------------------===//
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multiclass fma4s<bits<8> opc, string OpcodeStr> {
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multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop> {
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def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_W;
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def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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(ins VR128:$src1, VR128:$src2, memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_W;
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def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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(ins VR128:$src1, memop:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>;
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}
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multiclass fma4p<bits<8> opc, string OpcodeStr> {
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@ -151,20 +150,20 @@ multiclass fma4p<bits<8> opc, string OpcodeStr> {
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}
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let isAsmParserOnly = 1 in {
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defm VFMADDSS4 : fma4s<0x6A, "vfmaddss">;
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defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd">;
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defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem>;
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defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem>;
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defm VFMADDPS4 : fma4p<0x68, "vfmaddps">;
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defm VFMADDPD4 : fma4p<0x69, "vfmaddpd">;
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defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss">;
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defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd">;
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defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem>;
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defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem>;
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defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps">;
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defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd">;
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defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss">;
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defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd">;
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defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem>;
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defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem>;
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defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps">;
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defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd">;
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defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss">;
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defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd">;
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defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem>;
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defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem>;
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defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps">;
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defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd">;
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defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps">;
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@ -178,21 +177,17 @@ let isAsmParserOnly = 1 in {
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// VFMADD
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def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2,
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(alignedloadv4f32 addr:$src3)),
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(VFMADDSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
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VR128:$src3),
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(VFMADDSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
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(VFMADDSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
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(VFMADDSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2,
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(alignedloadv2f64 addr:$src3)),
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(VFMADDSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
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VR128:$src3),
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(VFMADDSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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(VFMADDSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFMADDSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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@ -235,21 +230,17 @@ def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1,
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// VFMSUB
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def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2,
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(alignedloadv4f32 addr:$src3)),
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(VFMSUBSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
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VR128:$src3),
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(VFMSUBSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
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(VFMSUBSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
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(VFMSUBSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2,
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(alignedloadv2f64 addr:$src3)),
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(VFMSUBSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
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VR128:$src3),
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(VFMSUBSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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(VFMSUBSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFMSUBSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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@ -292,21 +283,17 @@ def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1,
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// VFNMADD
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def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2,
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(alignedloadv4f32 addr:$src3)),
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(VFNMADDSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
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VR128:$src3),
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(VFNMADDSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
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(VFNMADDSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
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(VFNMADDSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2,
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(alignedloadv2f64 addr:$src3)),
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(VFNMADDSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
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VR128:$src3),
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(VFNMADDSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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(VFNMADDSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFNMADDSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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@ -349,21 +336,17 @@ def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1,
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// VFNMSUB
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def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2,
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(alignedloadv4f32 addr:$src3)),
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(VFNMSUBSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
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VR128:$src3),
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(VFNMSUBSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
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(VFNMSUBSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
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(VFNMSUBSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2,
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(alignedloadv2f64 addr:$src3)),
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(VFNMSUBSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
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VR128:$src3),
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(VFNMSUBSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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(VFNMSUBSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFNMSUBSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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@ -6,6 +6,20 @@ define < 4 x float > @test_x86_fma4_vfmadd_ss(< 4 x float > %a0, < 4 x float > %
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%res = call < 4 x float > @llvm.x86.fma4.vfmadd.ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) ; <i64> [#uses=1]
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ret < 4 x float > %res
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}
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define < 4 x float > @test_x86_fma4_vfmadd_ss_load(< 4 x float > %a0, < 4 x float > %a1, float* %a2) {
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; CHECK: vfmaddss (%{{.*}})
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%x = load float *%a2
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%y = insertelement <4 x float> undef, float %x, i32 0
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%res = call < 4 x float > @llvm.x86.fma4.vfmadd.ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %y) ; <i64> [#uses=1]
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ret < 4 x float > %res
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}
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define < 4 x float > @test_x86_fma4_vfmadd_ss_load2(< 4 x float > %a0, float* %a1, < 4 x float > %a2) {
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; CHECK: vfmaddss %{{.*}}, (%{{.*}})
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%x = load float *%a1
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%y = insertelement <4 x float> undef, float %x, i32 0
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%res = call < 4 x float > @llvm.x86.fma4.vfmadd.ss(< 4 x float > %a0, < 4 x float > %y, < 4 x float > %a2) ; <i64> [#uses=1]
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ret < 4 x float > %res
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}
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declare < 4 x float > @llvm.x86.fma4.vfmadd.ss(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone
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define < 2 x double > @test_x86_fma4_vfmadd_sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) {
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@ -13,6 +27,20 @@ define < 2 x double > @test_x86_fma4_vfmadd_sd(< 2 x double > %a0, < 2 x double
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%res = call < 2 x double > @llvm.x86.fma4.vfmadd.sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) ; <i64> [#uses=1]
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ret < 2 x double > %res
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}
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define < 2 x double > @test_x86_fma4_vfmadd_sd_load(< 2 x double > %a0, < 2 x double > %a1, double* %a2) {
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; CHECK: vfmaddsd (%{{.*}})
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%x = load double *%a2
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%y = insertelement <2 x double> undef, double %x, i32 0
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%res = call < 2 x double > @llvm.x86.fma4.vfmadd.sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %y) ; <i64> [#uses=1]
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ret < 2 x double > %res
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}
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define < 2 x double > @test_x86_fma4_vfmadd_sd_load2(< 2 x double > %a0, double* %a1, < 2 x double > %a2) {
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; CHECK: vfmaddsd %{{.*}}, (%{{.*}})
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%x = load double *%a1
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%y = insertelement <2 x double> undef, double %x, i32 0
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%res = call < 2 x double > @llvm.x86.fma4.vfmadd.sd(< 2 x double > %a0, < 2 x double > %y, < 2 x double > %a2) ; <i64> [#uses=1]
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ret < 2 x double > %res
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}
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declare < 2 x double > @llvm.x86.fma4.vfmadd.sd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone
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define < 4 x float > @test_x86_fma4_vfmadd_ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) {
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