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Silly bug

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27719 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-04-15 05:37:34 +00:00
parent 39fc145995
commit 57ebe9fbf0
3 changed files with 11 additions and 18 deletions
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5
lib/Target/X86/README.txt
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@ -810,8 +810,3 @@ destination?
How about andps, andpd, and pand? Do we really care about the type of the packed
elements? If not, why not always use the "ps" variants which are likely to be
shorter.
//===---------------------------------------------------------------------===//
Make sure XMM registers are spilled to 128-bit locations (if not already) and
add vector SSE opcodes to X86RegisterInfo::foldMemoryOperand().

22
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1724,27 +1724,26 @@ bool X86::isMOVSHDUPMask(SDNode *N) {
return false;
// Expect 1, 1, 3, 3
unsigned NumNodes = 0;
for (unsigned i = 0; i < 2; ++i) {
SDOperand Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
if (Val != 1) return false;
NumNodes++;
}
bool HasHi = false;
for (unsigned i = 2; i < 4; ++i) {
SDOperand Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
if (Val != 3) return false;
NumNodes++;
HasHi = true;
}
// Don't use movshdup if the resulting vector contains only one undef node.
// Use {p}shuf* instead.
return NumNodes > 1;
// Don't use movshdup if it can be done with a shufps.
return HasHi;
}
/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
@ -1756,27 +1755,26 @@ bool X86::isMOVSLDUPMask(SDNode *N) {
return false;
// Expect 0, 0, 2, 2
unsigned NumNodes = 0;
for (unsigned i = 0; i < 2; ++i) {
SDOperand Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
if (Val != 0) return false;
NumNodes++;
}
bool HasHi = false;
for (unsigned i = 2; i < 4; ++i) {
SDOperand Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
if (Val != 2) return false;
NumNodes++;
HasHi = true;
}
// Don't use movsldup if the resulting vector contains only one undef node.
// Use {p}shuf* instead.
return NumNodes > 1;
// Don't use movshdup if it can be done with a shufps.
return HasHi;
}
/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies

2
lib/Target/X86/X86InstrSSE.td
View File

@ -169,7 +169,7 @@ def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
// S3I - SSE3 instructions with TB and OpSize prefixes.
// S3SI - SSE3 instructions with XS prefix.
// S3SI - SSE3 instructions with XD prefix.
// S3DI - SSE3 instructions with XD prefix.
class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
: I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>