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https://github.com/c64scene-ar/llvm-6502.git
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ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
478849e98c
commit
580f4a9c1c
@ -395,12 +395,18 @@ def rot_imm : Operand<i32>, ImmLeaf<i32, [{
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}
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// shift_imm: An integer that encodes a shift amount and the type of shift
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// (currently either asr or lsl) using the same encoding used for the
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// immediates in so_reg operands.
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def ShifterAsmOperand : AsmOperandClass { let Name = "Shifter"; }
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// (asr or lsl). The 6-bit immediate encodes as:
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// {5} 0 ==> lsl
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// 1 asr
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// {4-0} imm5 shift amount.
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// asr #32 encoded as imm5 == 0.
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def ShifterImmAsmOperand : AsmOperandClass {
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let Name = "ShifterImm";
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let ParserMethod = "parseShifterImm";
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}
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def shift_imm : Operand<i32> {
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let PrintMethod = "printShiftImmOperand";
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let ParserMatchClass = ShifterAsmOperand;
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let ParserMatchClass = ShifterImmAsmOperand;
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}
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// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
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@ -2688,8 +2694,8 @@ def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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// Signed/Unsigned saturate -- for disassembly only
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def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$a, shift_imm:$sh),
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SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh", []> {
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def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn, shift_imm:$sh),
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SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
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bits<4> Rd;
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bits<5> sat_imm;
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bits<4> Rn;
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@ -2698,8 +2704,8 @@ def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$a, shift_imm:$sh),
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let Inst{5-4} = 0b01;
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let Inst{20-16} = sat_imm;
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let Inst{15-12} = Rd;
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let Inst{11-7} = sh{7-3};
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let Inst{6} = sh{0};
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let Inst{11-7} = sh{4-0};
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let Inst{6} = sh{5};
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let Inst{3-0} = Rn;
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}
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@ -2715,9 +2721,8 @@ def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn), SatFrm,
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let Inst{3-0} = Rn;
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}
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def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
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SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
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[/* For disassembly only; pattern left blank */]> {
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def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn, shift_imm:$sh),
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SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
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bits<4> Rd;
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bits<5> sat_imm;
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bits<4> Rn;
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@ -2725,8 +2730,8 @@ def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
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let Inst{27-21} = 0b0110111;
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let Inst{5-4} = 0b01;
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let Inst{15-12} = Rd;
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let Inst{11-7} = sh{7-3};
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let Inst{6} = sh{0};
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let Inst{11-7} = sh{4-0};
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let Inst{6} = sh{5};
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let Inst{20-16} = sat_imm;
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let Inst{3-0} = Rn;
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}
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@ -4278,3 +4283,7 @@ def : InstAlias<"rsc${s}${p} $Rdn, $shift",
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def : InstAlias<"rsc${s}${p} $Rdn, $shift",
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(RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
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cc_out:$s)>, Requires<[IsARM]>;
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// SSAT optional shift operand.
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def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
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(SSAT GPR:$Rd, imm1_32:$sat_imm, GPR:$Rn, 0, pred:$p)>;
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@ -1918,8 +1918,8 @@ class T2SatI<dag oops, dag iops, InstrItinClass itin,
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let Inst{11-8} = Rd;
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let Inst{19-16} = Rn;
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let Inst{4-0} = sat_imm{4-0};
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let Inst{21} = sh{6};
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let Inst{4-0} = sat_imm;
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let Inst{21} = sh{5};
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let Inst{14-12} = sh{4-2};
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let Inst{7-6} = sh{1-0};
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}
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@ -127,6 +127,7 @@ class ARMAsmParser : public TargetAsmParser {
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return parsePKHImm(O, "asr", 1, 32);
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}
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OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
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// Asm Match Converter Methods
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bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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@ -179,7 +180,7 @@ class ARMOperand : public MCParsedAsmOperand {
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SPRRegisterList,
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ShiftedRegister,
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ShiftedImmediate,
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Shifter,
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ShifterImmediate,
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Token
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} Kind;
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@ -239,9 +240,9 @@ class ARMOperand : public MCParsedAsmOperand {
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} Mem;
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struct {
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ARM_AM::ShiftOpc ShiftTy;
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bool isASR;
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unsigned Imm;
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} Shift;
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} ShifterImm;
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struct {
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ARM_AM::ShiftOpc ShiftTy;
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unsigned SrcReg;
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@ -296,8 +297,8 @@ public:
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case ProcIFlags:
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IFlags = o.IFlags;
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break;
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case Shifter:
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Shift = o.Shift;
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case ShifterImmediate:
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ShifterImm = o.ShifterImm;
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break;
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case ShiftedRegister:
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RegShiftedReg = o.RegShiftedReg;
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@ -505,7 +506,7 @@ public:
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bool isToken() const { return Kind == Token; }
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bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
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bool isMemory() const { return Kind == Memory; }
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bool isShifter() const { return Kind == Shifter; }
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bool isShifterImm() const { return Kind == ShifterImmediate; }
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bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
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bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
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bool isMemMode2() const {
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@ -656,10 +657,10 @@ public:
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}
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void addShifterOperands(MCInst &Inst, unsigned N) const {
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void addShifterImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateImm(
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ARM_AM::getSORegOpc(Shift.ShiftTy, 0)));
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Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
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ShifterImm.Imm));
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}
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void addRegListOperands(MCInst &Inst, unsigned N) const {
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@ -962,10 +963,11 @@ public:
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return Op;
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}
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static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy,
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static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
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SMLoc S, SMLoc E) {
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ARMOperand *Op = new ARMOperand(Shifter);
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Op->Shift.ShiftTy = ShTy;
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ARMOperand *Op = new ARMOperand(ShifterImmediate);
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Op->ShifterImm.isASR = isASR;
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Op->ShifterImm.Imm = Imm;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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@ -1127,8 +1129,9 @@ void ARMOperand::print(raw_ostream &OS) const {
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case Register:
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OS << "<register " << getReg() << ">";
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break;
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case Shifter:
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OS << "<shifter " << ARM_AM::getShiftOpcStr(Shift.ShiftTy) << ">";
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case ShifterImmediate:
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OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
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<< " #" << ShifterImm.Imm << ">";
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break;
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case ShiftedRegister:
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OS << "<so_reg_reg "
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@ -1705,6 +1708,73 @@ parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return MatchOperand_Success;
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}
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/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
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/// instructions. Legal values are:
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/// lsl #n 'n' in [0,31]
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/// asr #n 'n' in [1,32]
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/// n == 32 encoded as n == 0.
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ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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const AsmToken &Tok = Parser.getTok();
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SMLoc S = Tok.getLoc();
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if (Tok.isNot(AsmToken::Identifier)) {
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Error(S, "shift operator 'asr' or 'lsl' expected");
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return MatchOperand_ParseFail;
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}
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StringRef ShiftName = Tok.getString();
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bool isASR;
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if (ShiftName == "lsl" || ShiftName == "LSL")
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isASR = false;
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else if (ShiftName == "asr" || ShiftName == "ASR")
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isASR = true;
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else {
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Error(S, "shift operator 'asr' or 'lsl' expected");
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return MatchOperand_ParseFail;
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}
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Parser.Lex(); // Eat the operator.
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// A '#' and a shift amount.
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if (Parser.getTok().isNot(AsmToken::Hash)) {
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Error(Parser.getTok().getLoc(), "'#' expected");
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return MatchOperand_ParseFail;
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}
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Parser.Lex(); // Eat hash token.
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const MCExpr *ShiftAmount;
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SMLoc E = Parser.getTok().getLoc();
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if (getParser().ParseExpression(ShiftAmount)) {
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Error(E, "malformed shift expression");
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return MatchOperand_ParseFail;
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}
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
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if (!CE) {
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Error(E, "shift amount must be an immediate");
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return MatchOperand_ParseFail;
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}
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int64_t Val = CE->getValue();
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if (isASR) {
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// Shift amount must be in [1,32]
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if (Val < 1 || Val > 32) {
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Error(E, "'asr' shift amount must be in range [1,32]");
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return MatchOperand_ParseFail;
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}
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// asr #32 encoded as asr #0.
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if (Val == 32) Val = 0;
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} else {
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// Shift amount must be in [1,32]
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if (Val < 0 || Val > 31) {
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Error(E, "'lsr' shift amount must be in range [0,31]");
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return MatchOperand_ParseFail;
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}
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}
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E = Parser.getTok().getLoc();
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Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
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return MatchOperand_Success;
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}
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/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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@ -1732,17 +1732,11 @@ static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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decodeRm(insn))));
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if (NumOpsAdded == 4) {
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ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl);
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// Inst{6} encodes the shift type.
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bool isASR = slice(insn, 6, 6);
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// Inst{11-7} encodes the imm5 shift amount.
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unsigned ShAmt = slice(insn, 11, 7);
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if (ShAmt == 0) {
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// A8.6.183. Possible ASR shift amount of 32...
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if (Opc == ARM_AM::asr)
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ShAmt = 32;
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else
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Opc = ARM_AM::no_shift;
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}
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MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
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MI.addOperand(MCOperand::CreateImm(isASR << 5 | ShAmt));
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}
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return true;
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}
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@ -1615,17 +1615,11 @@ static bool DisassembleThumb2Sat(MCInst &MI, unsigned Opcode, uint32_t insn,
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decodeRn(insn))));
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if (NumOpsAdded == 4) {
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ARM_AM::ShiftOpc Opc = (slice(insn, 21, 21) != 0 ?
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ARM_AM::asr : ARM_AM::lsl);
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// Inst{14-12:7-6} encodes the imm5 shift amount.
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unsigned ShAmt = slice(insn, 14, 12) << 2 | slice(insn, 7, 6);
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if (ShAmt == 0) {
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if (Opc == ARM_AM::asr)
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ShAmt = 32;
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else
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Opc = ARM_AM::no_shift;
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}
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MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
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// Inst{6} encodes the shift type.
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bool isASR = slice(insn, 6, 6);
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// Inst{11-7} encodes the imm5 shift amount.
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unsigned ShAmt = slice(insn, 11, 7);
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MI.addOperand(MCOperand::CreateImm(isASR << 5 | ShAmt));
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}
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return true;
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}
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@ -450,20 +450,12 @@ void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
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void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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unsigned ShiftOp = MI->getOperand(OpNum).getImm();
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ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
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switch (Opc) {
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case ARM_AM::no_shift:
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return;
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case ARM_AM::lsl:
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O << ", lsl #";
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break;
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case ARM_AM::asr:
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O << ", asr #";
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break;
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default:
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assert(0 && "unexpected shift opcode for shift immediate operand");
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}
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O << ARM_AM::getSORegOffset(ShiftOp);
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bool isASR = (ShiftOp & (1 << 5)) != 0;
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unsigned Amt = ShiftOp & 0x1f;
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if (isASR)
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O << ", asr #" << (Amt == 0 ? 32 : Amt);
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else if (Amt)
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O << ", lsl #" << Amt;
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}
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void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
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@ -1614,6 +1614,23 @@ _func:
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@------------------------------------------------------------------------------
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@ FIXME: SRS
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@------------------------------------------------------------------------------
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@------------------------------------------------------------------------------
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@ SSAT
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@------------------------------------------------------------------------------
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ssat r8, #1, r10
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ssat r8, #1, r10, lsl #0
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ssat r8, #1, r10, lsl #31
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ssat r8, #1, r10, asr #32
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ssat r8, #1, r10, asr #1
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@ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6]
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@ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6]
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@ CHECK: ssat r8, #1, r10, lsl #31 @ encoding: [0x9a,0x8f,0xa0,0xe6]
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@ CHECK: ssat r8, #1, r10, asr #32 @ encoding: [0x5a,0x80,0xa0,0xe6]
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@ CHECK: ssat r8, #1, r10, asr #1 @ encoding: [0xda,0x80,0xa0,0xe6]
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@------------------------------------------------------------------------------
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@ STM*
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@------------------------------------------------------------------------------
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@ -160,3 +160,43 @@
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@ CHECK: error: 'be' or 'le' operand expected
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@ CHECK: setend 1
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@ CHECK: ^
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@ Out of range immediates and bad shift types for SSAT
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ssat r8, #0, r10, lsl #8
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ssat r8, #33, r10, lsl #8
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ssat r8, #1, r10, lsl #-1
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ssat r8, #1, r10, lsl #32
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ssat r8, #1, r10, asr #0
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ssat r8, #1, r10, asr #33
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ssat r8, #1, r10, lsr #5
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ssat r8, #1, r10, lsl fred
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ssat r8, #1, r10, lsl #fred
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@ CHECK: error: invalid operand for instruction
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@ CHECK: ssat r8, #0, r10, lsl #8
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@ CHECK: ^
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@ CHECK: error: invalid operand for instruction
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@ CHECK: ssat r8, #33, r10, lsl #8
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@ CHECK: ^
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@ CHECK: error: 'lsr' shift amount must be in range [0,31]
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@ CHECK: ssat r8, #1, r10, lsl #-1
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@ CHECK: ^
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@ CHECK: error: 'lsr' shift amount must be in range [0,31]
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@ CHECK: ssat r8, #1, r10, lsl #32
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@ CHECK: ^
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@ CHECK: error: 'asr' shift amount must be in range [1,32]
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@ CHECK: ssat r8, #1, r10, asr #0
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@ CHECK: ^
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@ CHECK: error: 'asr' shift amount must be in range [1,32]
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@ CHECK: ssat r8, #1, r10, asr #33
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@ CHECK: ^
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@ CHECK: error: shift operator 'asr' or 'lsl' expected
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@ CHECK: ssat r8, #1, r10, lsr #5
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@ CHECK: ^
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@ CHECK: error: '#' expected
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@ CHECK: ssat r8, #1, r10, lsl fred
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@ CHECK: ^
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@ CHECK: error: shift amount must be an immediate
|
||||
@ CHECK: ssat r8, #1, r10, lsl #fred
|
||||
@ CHECK: ^
|
||||
|
||||
Loading…
Reference in New Issue
Block a user