6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-01 15:11:24 +00:00
Code Issues Projects Releases Wiki Activity

Add missing builtins to the PPC back end for ABI compliance (vol. 4)

Browse Source 
This patch corresponds to review:
http://reviews.llvm.org/D11183

Back end portion of the fourth round of additions to altivec.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242167 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic 2015-07-14 17:25:20 +00:00
parent 18ec07dece
commit 582194d3b8
3 changed files with 42 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/IR/IntrinsicsPowerPC.td
View File

@ -694,6 +694,12 @@ def int_ppc_vsx_xvrspip :
def int_ppc_vsx_xvrdpip :
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
// Vector reciprocal estimate
def int_ppc_vsx_xvresp : GCCBuiltin<"__builtin_vsx_xvresp">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_ppc_vsx_xvredp : GCCBuiltin<"__builtin_vsx_xvredp">,
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
// Vector rsqrte
def int_ppc_vsx_xvrsqrtesp : GCCBuiltin<"__builtin_vsx_xvrsqrtesp">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;

6
lib/Target/PowerPC/PPCInstrVSX.td
View File

@ -989,6 +989,12 @@ def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
(XVDIVDP $A, $B)>;
// Reciprocal estimate
def : Pat<(int_ppc_vsx_xvresp v4f32:$A),
(XVRESP $A)>;
def : Pat<(int_ppc_vsx_xvredp v2f64:$A),
(XVREDP $A)>;
// Recip. square root estimate
def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
(XVRSQRTESP $A)>;

30
test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll
View File

@ -134,6 +134,36 @@ entry:
; CHECK: xvcmpgtsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
}
; Function Attrs: nounwind
define <4 x float> @emit_xvresp(<4 x float> %a) {
entry:
%a.addr = alloca <4 x float>, align 16
store <4 x float> %a, <4 x float>* %a.addr, align 16
%0 = load <4 x float>, <4 x float>* %a.addr, align 16
%1 = call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float> %0)
ret <4 x float> %1
; CHECK-LABEL: @emit_xvresp
; CHECK: xvresp {{[0-9]+}}, {{[0-9]+}}
}
; Function Attrs: nounwind
define <2 x double> @emit_xvredp(<2 x double> %a) {
entry:
%a.addr = alloca <2 x double>, align 16
store <2 x double> %a, <2 x double>* %a.addr, align 16
%0 = load <2 x double>, <2 x double>* %a.addr, align 16
%1 = call <2 x double> @llvm.ppc.vsx.xvredp(<2 x double> %0)
ret <2 x double> %1
; CHECK-LABEL: @emit_xvredp
; CHECK: xvredp {{[0-9]+}}, {{[0-9]+}}
}
; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)
; Function Attrs: nounwind readnone
declare <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>)
; Function Attrs: nounwind readnone
declare <2 x double> @llvm.ceil.v2f64(<2 x double>)