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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
Remove some redundant instruction classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99187 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
50fc9f319e
commit
58393bc3fd
@ -190,46 +190,43 @@ let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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class VLD1D3<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3\\}, $addr", "",
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[/* For disassembly only; pattern left blank */]>;
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"\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
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class VLD1D4<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "",
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[/* For disassembly only; pattern left blank */]>;
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
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def VLD1d8T : VLD1D3<0b0000, "8">;
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def VLD1d16T : VLD1D3<0b0100, "16">;
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def VLD1d32T : VLD1D3<0b1000, "32">;
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// VLD1d64T : implemented as VLD3d64
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def VLD3d64 : VLD1D3<0b1100, "64">;
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def VLD1d8Q : VLD1D4<0b0000, "8">;
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def VLD1d16Q : VLD1D4<0b0100, "16">;
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def VLD1d32Q : VLD1D4<0b1000, "32">;
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// VLD1d64Q : implemented as VLD4d64
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def VLD4d64 : VLD1D4<0b1100, "64">;
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// ...with address register writeback:
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class VLD1D3WB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb",
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[/* For disassembly only; pattern left blank */]>;
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"\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
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class VLD1D4WB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0010,op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
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[/* For disassembly only; pattern left blank */]>;
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[]>;
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def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
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def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
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def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
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// VLD1d64T_UPD : implemented as VLD3d64_UPD
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def VLD3d64_UPD : VLD1D3WB<0b1100, "64">;
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def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
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def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
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def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
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// VLD1d64Q_UPD : implemented as VLD4d64_UPD
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def VLD4d64_UPD : VLD1D4WB<0b1100, "64">;
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// VLD2 : Vector Load (multiple 2-element structures)
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class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -296,10 +293,6 @@ class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
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def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
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def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
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def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
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def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr), IIC_VLD1,
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"vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
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// ...with address register writeback:
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class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -312,11 +305,6 @@ class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
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def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
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def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
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def VLD3d64_UPD : NLdSt<0,0b10,0b0110,0b1100,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
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"vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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// ...with double-spaced registers (non-updating versions for disassembly only):
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def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
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@ -341,11 +329,6 @@ class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
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def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
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def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
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def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
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def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD1,
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"vld1", "64", "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
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"", []>;
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// ...with address register writeback:
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class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -358,13 +341,6 @@ class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
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def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
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def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
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def VLD4d64_UPD : NLdSt<0,0b10,0b0010,0b1100,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4,
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GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
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"vld1", "64",
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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// ...with double-spaced registers (non-updating versions for disassembly only):
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def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
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@ -550,23 +526,22 @@ def VST1q64_UPD : VST1QWB<0b1100, "64">;
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class VST1D3<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0110, op7_4, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "",
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[/* For disassembly only; pattern left blank */]>;
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
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class VST1D4<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0010, op7_4, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
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[/* For disassembly only; pattern left blank */]>;
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[]>;
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def VST1d8T : VST1D3<0b0000, "8">;
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def VST1d16T : VST1D3<0b0100, "16">;
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def VST1d32T : VST1D3<0b1000, "32">;
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// VST1d64T : implemented as VST3d64
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def VST3d64 : VST1D3<0b1100, "64">;
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def VST1d8Q : VST1D4<0b0000, "8">;
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def VST1d16Q : VST1D4<0b0100, "16">;
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def VST1d32Q : VST1D4<0b1000, "32">;
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// VST1d64Q : implemented as VST4d64
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def VST4d64 : VST1D4<0b1100, "64">;
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// ...with address register writeback:
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class VST1D3WB<bits<4> op7_4, string Dt>
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@ -574,25 +549,23 @@ class VST1D3WB<bits<4> op7_4, string Dt>
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(ins addrmode6:$addr, am6offset:$offset,
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DPR:$src1, DPR:$src2, DPR:$src3),
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
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"$addr.addr = $wb",
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[/* For disassembly only; pattern left blank */]>;
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"$addr.addr = $wb", []>;
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class VST1D4WB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset,
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DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
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"$addr.addr = $wb",
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[/* For disassembly only; pattern left blank */]>;
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"$addr.addr = $wb", []>;
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def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
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def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
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def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
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// VST1d64T_UPD : implemented as VST3d64_UPD
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def VST3d64_UPD : VST1D3WB<0b1100, "64">;
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def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
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def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
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def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
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// VST1d64Q_UPD : implemented as VST4d64_UPD
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def VST4d64_UPD : VST1D4WB<0b1100, "64">;
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// VST2 : Vector Store (multiple 2-element structures)
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class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -659,10 +632,6 @@ class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
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def VST3d8 : VST3D<0b0100, 0b0000, "8">;
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def VST3d16 : VST3D<0b0100, 0b0100, "16">;
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def VST3d32 : VST3D<0b0100, 0b1000, "32">;
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def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
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IIC_VST,
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"vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
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// ...with address register writeback:
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class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -675,11 +644,6 @@ class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
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def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
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def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
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def VST3d64_UPD : NLdSt<0,0b00,0b0110,0b1100, (outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset,
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DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
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"vst1", "64", "\\{$src1, $src2, $src3\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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// ...with double-spaced registers (non-updating versions for disassembly only):
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def VST3q8 : VST3D<0b0101, 0b0000, "8">;
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@ -704,11 +668,6 @@ class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
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def VST4d8 : VST4D<0b0000, 0b0000, "8">;
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def VST4d16 : VST4D<0b0000, 0b0100, "16">;
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def VST4d32 : VST4D<0b0000, 0b1000, "32">;
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def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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DPR:$src4), IIC_VST,
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"vst1", "64", "\\{$src1, $src2, $src3, $src4\\}, $addr",
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"", []>;
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// ...with address register writeback:
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class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -721,12 +680,6 @@ class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
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def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
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def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
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def VST4d64_UPD : NLdSt<0,0b00,0b0010,0b1100, (outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset,
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DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
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"vst1", "64",
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"\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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// ...with double-spaced registers (non-updating versions for disassembly only):
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def VST4q8 : VST4D<0b0001, 0b0000, "8">;
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