diff --git a/lib/Target/PowerPC/PPC32.td b/lib/Target/PowerPC/PPC32.td index fb115f43129..15ff2446350 100644 --- a/lib/Target/PowerPC/PPC32.td +++ b/lib/Target/PowerPC/PPC32.td @@ -24,9 +24,8 @@ include "PowerPCInstrInfo.td" def PowerPCInstrInfo : InstrInfo { let PHIInst = PHI; - let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", - "Arg3Type", "Arg4Type", "VMX", "PPC64"]; - let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ]; + let TSFlagsFields = [ "VMX", "PPC64" ]; + let TSFlagsShifts = [ 0, 1 ]; let isLittleEndianEncoding = 1; } diff --git a/lib/Target/PowerPC/PPC64.td b/lib/Target/PowerPC/PPC64.td index 06067ed1f41..16f20e868bb 100644 --- a/lib/Target/PowerPC/PPC64.td +++ b/lib/Target/PowerPC/PPC64.td @@ -24,9 +24,8 @@ include "PowerPCInstrInfo.td" def PowerPCInstrInfo : InstrInfo { let PHIInst = PHI; - let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", - "Arg3Type", "Arg4Type", "VMX", "PPC64"]; - let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ]; + let TSFlagsFields = [ "VMX", "PPC64" ]; + let TSFlagsShifts = [ 0, 1 ]; let isLittleEndianEncoding = 1; } diff --git a/lib/Target/PowerPC/PowerPC.td b/lib/Target/PowerPC/PowerPC.td index b7d5bf116f8..0d3ab21ff31 100644 --- a/lib/Target/PowerPC/PowerPC.td +++ b/lib/Target/PowerPC/PowerPC.td @@ -24,9 +24,8 @@ include "PowerPCInstrInfo.td" def PowerPCInstrInfo : InstrInfo { let PHIInst = PHI; - let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", - "Arg3Type", "Arg4Type", "VMX", "PPC64"]; - let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ]; + let TSFlagsFields = [ "VMX", "PPC64" ]; + let TSFlagsShifts = [ 0, 1 ]; let isLittleEndianEncoding = 1; } diff --git a/lib/Target/PowerPC/PowerPCInstrInfo.h b/lib/Target/PowerPC/PowerPCInstrInfo.h index 29940d65ee0..e0651ba8f43 100644 --- a/lib/Target/PowerPC/PowerPCInstrInfo.h +++ b/lib/Target/PowerPC/PowerPCInstrInfo.h @@ -18,49 +18,38 @@ #include "llvm/Target/TargetInstrInfo.h" namespace llvm { - -namespace PPCII { - enum { - ArgCountShift = 0, - ArgCountMask = 7, - - Arg0TypeShift = 3, - Arg1TypeShift = 8, - Arg2TypeShift = 13, - Arg3TypeShift = 18, - Arg4TypeShift = 23, - VMX = 1<<28, - PPC64 = 1<<29, - ArgTypeMask = 31 - }; - - enum { - None = 0, - Gpr = 1, - Gpr0 = 2, - Simm16 = 3, - Zimm16 = 4, - PCRelimm24 = 5, - Imm24 = 6, - Imm5 = 7, - PCRelimm14 = 8, - Imm14 = 9, - Imm2 = 10, - Crf = 11, - Imm3 = 12, - Imm1 = 13, - Fpr = 14, - Imm4 = 15, - Imm8 = 16, - Disimm16 = 17, - Disimm14 = 18, - Spr = 19, - Sgr = 20, - Imm15 = 21, - Vpr = 22 - }; -} - + namespace PPCII { + enum { + VMX = 1 << 0, + PPC64 = 1 << 1, + }; + + enum { + None = 0, + Gpr = 1, + Gpr0 = 2, + Simm16 = 3, + Zimm16 = 4, + PCRelimm24 = 5, + Imm24 = 6, + Imm5 = 7, + PCRelimm14 = 8, + Imm14 = 9, + Imm2 = 10, + Crf = 11, + Imm3 = 12, + Imm1 = 13, + Fpr = 14, + Imm4 = 15, + Imm8 = 16, + Disimm16 = 17, + Disimm14 = 18, + Spr = 19, + Sgr = 20, + Imm15 = 21, + Vpr = 22 + }; + } } #endif