From 5874f82564d6cd9da086cc705e1c5c8ec8ff8361 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 8 Mar 2006 04:37:58 +0000 Subject: [PATCH] remove "Slot", it is dead git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26609 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 27 ++++++++- lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp | 63 ++++++++++---------- 2 files changed, 56 insertions(+), 34 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 5c3787e35f2..a6d74c85e7c 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1795,10 +1795,33 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Custom: Tmp1 = TLI.LowerOperation(Result, DAG); if (Tmp1.Val) Result = Tmp1; - break; + break; case TargetLowering::Legal: break; case TargetLowering::Expand: - // Floating point mod -> fmod libcall. + // If this target supports fabs/fneg natively, do this efficiently. + if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) && + TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) { + // Get the sign bit of the RHS. + MVT::ValueType IVT = + Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; + SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); + SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), + SignBit, DAG.getConstant(0, IVT), ISD::SETLT); + // Get the absolute value of the result. + SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); + // Select between the nabs and abs value based on the sign bit of + // the input. + Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, + DAG.getNode(ISD::FNEG, AbsVal.getValueType(), + AbsVal), + AbsVal); + Result = LegalizeOp(Result); + break; + } + + // Otherwise, do bitwise ops! + + // copysign -> copysignf/copysign libcall. const char *FnName; if (Node->getValueType(0) == MVT::f32) { FnName = "copysignf"; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index e089d0bc0f6..b39ab7f607c 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -20,7 +20,6 @@ #define DEBUG_TYPE "sched" #include "llvm/CodeGen/ScheduleDAG.h" -#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/Debug.h" @@ -36,36 +35,36 @@ namespace { Statistic<> NumNoops ("scheduler", "Number of noops inserted"); Statistic<> NumStalls("scheduler", "Number of pipeline stalls"); -/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or a -/// group of nodes flagged together. -struct SUnit { - SDNode *Node; // Representative node. - std::vector FlaggedNodes; // All nodes flagged to Node. - std::set Preds; // All real predecessors. - std::set ChainPreds; // All chain predecessors. - std::set Succs; // All real successors. - std::set ChainSuccs; // All chain successors. - int NumPredsLeft; // # of preds not scheduled. - int NumSuccsLeft; // # of succs not scheduled. - int NumChainPredsLeft; // # of chain preds not scheduled. - int NumChainSuccsLeft; // # of chain succs not scheduled. - int SethiUllman; // Sethi Ullman number. - bool isTwoAddress; // Is a two-address instruction. - bool isDefNUseOperand; // Is a def&use operand. - unsigned Latency; // Node latency. - unsigned CycleBound; // Upper/lower cycle to be scheduled at. - unsigned Slot; // Cycle node is scheduled at. - SUnit *Next; - - SUnit(SDNode *node) - : Node(node), NumPredsLeft(0), NumSuccsLeft(0), + /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or a + /// group of nodes flagged together. + struct SUnit { + SDNode *Node; // Representative node. + std::vector FlaggedNodes; // All nodes flagged to Node. + std::set Preds; // All real predecessors. + std::set ChainPreds; // All chain predecessors. + std::set Succs; // All real successors. + std::set ChainSuccs; // All chain successors. + int NumPredsLeft; // # of preds not scheduled. + int NumSuccsLeft; // # of succs not scheduled. + int NumChainPredsLeft; // # of chain preds not scheduled. + int NumChainSuccsLeft; // # of chain succs not scheduled. + int SethiUllman; // Sethi Ullman number. + bool isTwoAddress; // Is a two-address instruction. + bool isDefNUseOperand; // Is a def&use operand. + unsigned Latency; // Node latency. + unsigned CycleBound; // Upper/lower cycle to be scheduled at. + SUnit *Next; + + SUnit(SDNode *node) + : Node(node), NumPredsLeft(0), NumSuccsLeft(0), NumChainPredsLeft(0), NumChainSuccsLeft(0), SethiUllman(INT_MIN), isTwoAddress(false), isDefNUseOperand(false), - Latency(0), CycleBound(0), Slot(0), Next(NULL) {} - - void dump(const SelectionDAG *G, bool All=true) const; -}; + Latency(0), CycleBound(0), Next(NULL) {} + + void dump(const SelectionDAG *G, bool All=true) const; + }; +} void SUnit::dump(const SelectionDAG *G, bool All) const { std::cerr << "SU: "; @@ -122,6 +121,7 @@ void SUnit::dump(const SelectionDAG *G, bool All) const { } } +namespace { /// Sorting functions for the Available queue. struct ls_rr_sort : public std::binary_function { bool operator()(const SUnit* left, const SUnit* right) const { @@ -159,8 +159,10 @@ struct ls_rr_sort : public std::binary_function { return false; } }; +} // end anonymous namespace +namespace { /// ScheduleDAGList - List scheduler. class ScheduleDAGList : public ScheduleDAG { private: @@ -219,7 +221,7 @@ private: void BuildSchedUnits(); void EmitSchedule(); }; -} // end namespace +} // end anonymous namespace HazardRecognizer::~HazardRecognizer() {} @@ -305,7 +307,6 @@ void ScheduleDAGList::ScheduleNodeBottomUp(AvailableQueueTy &Available, DEBUG(SU->dump(&DAG, false)); Sequence.push_back(SU); - SU->Slot = CurrCycle; // Bottom up: release predecessors for (std::set::iterator I1 = SU->Preds.begin(), @@ -329,7 +330,6 @@ void ScheduleDAGList::ScheduleNodeTopDown(AvailableQueueTy &Available, DEBUG(SU->dump(&DAG, false)); Sequence.push_back(SU); - SU->Slot = CurrCycle; // Bottom up: release successors. for (std::set::iterator I1 = SU->Succs.begin(), @@ -384,7 +384,6 @@ void ScheduleDAGList::ListScheduleBottomUp() { // Add entry node last if (DAG.getEntryNode().Val != DAG.getRoot().Val) { SUnit *Entry = SUnitMap[DAG.getEntryNode().Val]; - Entry->Slot = CurrCycle; Sequence.push_back(Entry); }