From 587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Wed, 13 May 2009 21:33:08 +0000 Subject: [PATCH] Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/CodeGenerator.html | 2 +- include/llvm/CodeGen/MachineInstrBuilder.h | 56 ++++++++++++---- lib/CodeGen/TargetInstrInfoImpl.cpp | 6 +- lib/Target/ARM/ARMInstrInfo.cpp | 26 ++++---- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 19 +++--- lib/Target/ARM/ARMRegisterInfo.cpp | 30 ++++----- lib/Target/Alpha/AlphaInstrInfo.cpp | 12 ++-- lib/Target/CellSPU/SPUInstrInfo.cpp | 8 +-- lib/Target/IA64/IA64InstrInfo.cpp | 8 +-- lib/Target/MSP430/MSP430InstrInfo.cpp | 6 +- lib/Target/MSP430/MSP430RegisterInfo.cpp | 2 +- lib/Target/Mips/MipsInstrInfo.cpp | 12 ++-- lib/Target/PIC16/PIC16InstrInfo.cpp | 4 +- lib/Target/PowerPC/PPCInstrInfo.cpp | 64 +++++++++++++------ lib/Target/PowerPC/PPCRegisterInfo.cpp | 40 ++++++------ lib/Target/Sparc/SparcInstrInfo.cpp | 12 ++-- lib/Target/X86/X86InstrBuilder.h | 8 +-- lib/Target/X86/X86InstrInfo.cpp | 74 ++++++++++++++-------- lib/Target/X86/X86RegisterInfo.cpp | 4 +- lib/Target/XCore/XCoreInstrInfo.cpp | 2 +- lib/Target/XCore/XCoreRegisterInfo.cpp | 12 ++-- 21 files changed, 242 insertions(+), 165 deletions(-) diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index dd9cd4a45ba..9a28f1f0ca3 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -600,7 +600,7 @@ BuildMI(MBB, X86::JNE, 1).addMBB(&MBB); 
-MI.addReg(Reg, MachineOperand::Def);
+MI.addReg(Reg, RegState::Define);
diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h index de27bc74eef..d3a09959a1b 100644 --- a/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/include/llvm/CodeGen/MachineInstrBuilder.h @@ -23,6 +23,18 @@ namespace llvm { class TargetInstrDesc; +namespace RegState { + enum { + Define = 0x2, + Implicit = 0x4, + Kill = 0x8, + Dead = 0x10, + EarlyClobber = 0x20, + ImplicitDefine = Implicit | Define, + ImplicitKill = Implicit | Kill + }; +} + class MachineInstrBuilder { MachineInstr *MI; public: @@ -36,12 +48,17 @@ public: /// addReg - Add a new virtual register operand... /// const - MachineInstrBuilder &addReg(unsigned RegNo, bool isDef = false, - bool isImp = false, bool isKill = false, - bool isDead = false, unsigned SubReg = 0, - bool isEarlyClobber = false) const { - MI->addOperand(MachineOperand::CreateReg(RegNo, isDef, isImp, isKill, - isDead, SubReg, isEarlyClobber)); + MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0, + unsigned SubReg = 0) const { + assert((flags & 0x1) == 0 && + "Passing in 'true' to addReg is forbidden! Use enums instead."); + MI->addOperand(MachineOperand::CreateReg(RegNo, + flags & RegState::Define, + flags & RegState::Implicit, + flags & RegState::Kill, + flags & RegState::Dead, + SubReg, + flags & RegState::EarlyClobber)); return *this; } @@ -97,9 +114,13 @@ public: const MachineInstrBuilder &addOperand(const MachineOperand &MO) const { if (MO.isReg()) - return addReg(MO.getReg(), MO.isDef(), MO.isImplicit(), - MO.isKill(), MO.isDead(), MO.getSubReg(), - MO.isEarlyClobber()); + return addReg(MO.getReg(), + (MO.isDef() ? RegState::Define : 0) | + (MO.isImplicit() ? RegState::Implicit : 0) | + (MO.isKill() ? RegState::Kill : 0) | + (MO.isDead() ? RegState::Dead : 0) | + (MO.isEarlyClobber() ? RegState::EarlyClobber : 0), + MO.getSubReg()); if (MO.isImm()) return addImm(MO.getImm()); if (MO.isFI()) @@ -135,7 +156,7 @@ inline MachineInstrBuilder BuildMI(MachineFunction &MF, const TargetInstrDesc &TID, unsigned DestReg) { return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)) - .addReg(DestReg, true); + .addReg(DestReg, RegState::Define); } /// BuildMI - This version of the builder inserts the newly-built @@ -149,7 +170,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, unsigned DestReg) { MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); BB.insert(I, MI); - return MachineInstrBuilder(MI).addReg(DestReg, true); + return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define); } /// BuildMI - This version of the builder inserts the newly-built @@ -186,6 +207,19 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, return BuildMI(*BB, BB->end(), DL, TID, DestReg); } +inline unsigned getDefRegState(bool B) { + return B ? RegState::Define : 0; +} +inline unsigned getImplRegState(bool B) { + return B ? RegState::Implicit : 0; +} +inline unsigned getKillRegState(bool B) { + return B ? RegState::Kill : 0; +} +inline unsigned getDeadRegState(bool B) { + return B ? RegState::Dead : 0; +} + } // End llvm namespace #endif diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp index a213400dcbd..a5e1ee43552 100644 --- a/lib/CodeGen/TargetInstrInfoImpl.cpp +++ b/lib/CodeGen/TargetInstrInfoImpl.cpp @@ -45,9 +45,9 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, bool Reg0IsDead = MI->getOperand(0).isDead(); MachineFunction &MF = *MI->getParent()->getParent(); return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) - .addReg(Reg0, true, false, false, Reg0IsDead) - .addReg(Reg2, false, false, Reg2IsKill) - .addReg(Reg1, false, false, Reg1IsKill); + .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) + .addReg(Reg2, getKillRegState(Reg2IsKill)) + .addReg(Reg1, getKillRegState(Reg2IsKill)); } if (ChangeReg0) diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 235d1d1d50d..8e678a8c461 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -546,23 +546,23 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, ARMFunctionInfo *AFI = MF.getInfo(); assert (!AFI->isThumbFunction()); AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addReg(0).addImm(0)); } else if (RC == ARM::tGPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); assert (AFI->isThumbFunction()); BuildMI(MBB, I, DL, get(ARM::tSpill)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0); } else if (RC == ARM::DPRRegisterClass) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0)); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0)); } } @@ -579,7 +579,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, if (AFI->isThumbFunction()) { Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR; MachineInstrBuilder MIB = - BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); NewMIs.push_back(MIB); @@ -594,7 +594,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } MachineInstrBuilder MIB = - BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); AddDefaultPred(MIB); @@ -681,7 +681,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, unsigned Reg = CSI[i-1].getReg(); // Add the callee-saved register as live-in. It's killed at the spill. MBB.addLiveIn(Reg); - MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/); + MIB.addReg(Reg, RegState::Kill); } return true; } @@ -733,13 +733,13 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) - .addReg(DstReg, true, false, false, isDead) + .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -755,7 +755,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, // tSpill cannot take a high register operand. break; NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); @@ -764,7 +764,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, break; bool isDead = MI->getOperand(0).isDead(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) - .addReg(DstReg, true, false, false, isDead) + .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) .addFrameIndex(FI).addImm(0); } break; @@ -792,13 +792,13 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) - .addReg(DstReg, true, false, false, isDead) + .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } break; diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 710bc3e90ef..047552f627d 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -159,7 +159,7 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, return false; // Probably not worth it then. BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase) - .addReg(Base, false, false, BaseKill).addImm(ImmedOffset) + .addReg(Base, getKillRegState(BaseKill)).addImm(ImmedOffset) .addImm(Pred).addReg(PredReg).addReg(0); Base = NewBase; BaseKill = true; // New base is always killed right its use. @@ -170,14 +170,15 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Opcode = getLoadStoreMultipleOpcode(Opcode); MachineInstrBuilder MIB = (isAM4) ? BuildMI(MBB, MBBI, dl, TII->get(Opcode)) - .addReg(Base, false, false, BaseKill) + .addReg(Base, getKillRegState(BaseKill)) .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg) : BuildMI(MBB, MBBI, dl, TII->get(Opcode)) - .addReg(Base, false, false, BaseKill) + .addReg(Base, getKillRegState(BaseKill)) .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs)) .addImm(Pred).addReg(PredReg); for (unsigned i = 0; i != NumRegs; ++i) - MIB = MIB.addReg(Regs[i].first, isDef, false, Regs[i].second); + MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) + | getKillRegState(Regs[i].second)); return true; } @@ -516,26 +517,26 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB, if (isAM2) // LDR_PRE, LDR_POST; BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) - .addReg(Base, true) + .addReg(Base, RegState::Define) .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); else // FLDMS, FLDMD BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) - .addReg(Base, false, false, BaseKill) + .addReg(Base, getKillRegState(BaseKill)) .addImm(Offset).addImm(Pred).addReg(PredReg) - .addReg(MI->getOperand(0).getReg(), true); + .addReg(MI->getOperand(0).getReg(), RegState::Define); } else { MachineOperand &MO = MI->getOperand(0); if (isAM2) // STR_PRE, STR_POST; BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base) - .addReg(MO.getReg(), false, false, MO.isKill()) + .addReg(MO.getReg(), getKillRegState(BaseKill)) .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); else // FSTMS, FSTMD BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset) .addImm(Pred).addReg(PredReg) - .addReg(MO.getReg(), false, false, MO.isKill()); + .addReg(MO.getReg(), getKillRegState(MO.isKill())); } MBB.erase(MBBI); diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 2fae432633b..693d12ee1f3 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -368,7 +368,7 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB, // Build the new ADD / SUB. BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) - .addReg(BaseReg, false, false, true).addImm(SOImmVal) + .addReg(BaseReg, RegState::Kill).addImm(SOImmVal) .addImm((unsigned)Pred).addReg(PredReg).addReg(0); BaseReg = DestReg; } @@ -426,7 +426,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, assert(BaseReg == ARM::SP && "Unexpected!"); LdReg = ARM::R3; BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12) - .addReg(ARM::R3, false, false, true); + .addReg(ARM::R3, RegState::Kill); } if (NumBytes <= 255 && NumBytes >= 0) @@ -434,7 +434,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, else if (NumBytes < 0 && NumBytes >= -255) { BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg) - .addReg(LdReg, false, false, true); + .addReg(LdReg, RegState::Kill); } else MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII, true, dl); @@ -444,12 +444,12 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); if (DestReg == ARM::SP || isSub) - MIB.addReg(BaseReg).addReg(LdReg, false, false, true); + MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); else - MIB.addReg(LdReg).addReg(BaseReg, false, false, true); + MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); if (DestReg == ARM::SP) BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3) - .addReg(ARM::R12, false, false, true); + .addReg(ARM::R12, RegState::Kill); } /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize @@ -518,10 +518,10 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; Bytes -= ThisVal; BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) - .addReg(BaseReg, false, false, true).addImm(ThisVal); + .addReg(BaseReg, RegState::Kill).addImm(ThisVal); } else { BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) - .addReg(BaseReg, false, false, true); + .addReg(BaseReg, RegState::Kill); } BaseReg = DestReg; } @@ -538,7 +538,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, else { bool isKill = BaseReg != ARM::SP; BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) - .addReg(BaseReg, false, false, isKill).addImm(ThisVal); + .addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal); BaseReg = DestReg; if (Opc == ARM::tADDrSPi) { @@ -556,7 +556,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, if (ExtraOpc) BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg) - .addReg(DestReg, false, false, true) + .addReg(DestReg, RegState::Kill) .addImm(((unsigned)NumBytes) & 3); } @@ -631,7 +631,7 @@ static void emitThumbConstant(MachineBasicBlock &MBB, emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl); if (isSub) BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg) - .addReg(DestReg, false, false, true); + .addReg(DestReg, RegState::Kill); } /// findScratchRegister - Find a 'free' ARM register. If register scavenger @@ -918,12 +918,12 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, bool UseRR = false; if (ValReg == ARM::R3) { BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12) - .addReg(ARM::R2, false, false, true); + .addReg(ARM::R2, RegState::Kill); TmpReg = ARM::R2; } if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12) - .addReg(ARM::R3, false, false, true); + .addReg(ARM::R3, RegState::Kill); if (Opcode == ARM::tSpill) { if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, @@ -946,10 +946,10 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineBasicBlock::iterator NII = next(II); if (ValReg == ARM::R3) BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2) - .addReg(ARM::R12, false, false, true); + .addReg(ARM::R12, RegState::Kill); if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3) - .addReg(ARM::R12, false, false, true); + .addReg(ARM::R12, RegState::Kill); } else assert(false && "Unexpected opcode!"); } else { diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 27408e2c799..a54d97d33c4 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -187,15 +187,15 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, if (RC == Alpha::F4RCRegisterClass) BuildMI(MBB, MI, DL, get(Alpha::STS)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) BuildMI(MBB, MI, DL, get(Alpha::STT)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) BuildMI(MBB, MI, DL, get(Alpha::STQ)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); @@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, abort(); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = - BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); NewMIs.push_back(MIB); @@ -290,7 +290,7 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(InReg, false, false, isKill) + .addReg(InReg, getKillRegState(isKill)) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move @@ -299,7 +299,7 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(OutReg, true, false, false, isDead) + .addReg(OutReg, RegState::Define | getDeadRegState(isDead)) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 135164f3d96..92ca244ed40 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -320,7 +320,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, DebugLoc DL = DebugLoc::getUnknownLoc(); if (MI != MBB.end()) DL = MI->getDebugLoc(); addFrameReference(BuildMI(MBB, MI, DL, get(opc)) - .addReg(SrcReg, false, false, isKill), FrameIdx); + .addReg(SrcReg, getKillRegState(isKill)), FrameIdx); } void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -353,7 +353,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); NewMIs.push_back(MIB); @@ -495,7 +495,7 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(SPU::STQDr32)); - MIB.addReg(InReg, false, false, isKill); + MIB.addReg(InReg, getKillRegState(isKill)); NewMI = addFrameReference(MIB, FrameIndex); } } else { // move -> load @@ -503,7 +503,7 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, bool isDead = MI->getOperand(0).isDead(); MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)); - MIB.addReg(OutReg, true, false, false, isDead); + MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead)); Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32; NewMI = addFrameReference(MIB, FrameIndex); diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index 65eff25261f..5f89d4f1399 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -96,17 +96,17 @@ void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, if (RC == IA64::FPRegisterClass) { BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); } else if (RC == IA64::GRRegisterClass) { BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); } else if (RC == IA64::PRRegisterClass) { /* we use IA64::r2 as a temporary register for doing this hackery. */ // first we load 0: BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0); // then conditionally add 1: BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) - .addImm(1).addReg(SrcReg, false, false, isKill); + .addImm(1).addReg(SrcReg, getKillRegState(isKill)); // and then store it to the stack BuildMI(MBB, MI, DL, get(IA64::ST8)) .addFrameIndex(FrameIdx) @@ -136,7 +136,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); - MIB.addReg(SrcReg, false, false, isKill); + MIB.addReg(SrcReg, getKillRegState(isKill)); NewMIs.push_back(MIB); return; diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp index 39c835d92f6..91112c3d732 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -38,11 +38,11 @@ void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, if (RC == &MSP430::GR16RegClass) BuildMI(MBB, MI, DL, get(MSP430::MOV16mr)) .addFrameIndex(FrameIdx).addImm(0) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); else if (RC == &MSP430::GR8RegClass) BuildMI(MBB, MI, DL, get(MSP430::MOV8mr)) .addFrameIndex(FrameIdx).addImm(0) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); else assert(0 && "Cannot store this register to stack slot!"); } @@ -129,7 +129,7 @@ MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, // Add the callee-saved register as live-in. It's killed at the spill. MBB.addLiveIn(Reg); BuildMI(MBB, MI, DL, get(MSP430::PUSH16r)) - .addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); + .addReg(Reg, RegState::Kill); } return true; } diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp index ebd09fb78e5..ef6f99756c2 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -241,7 +241,7 @@ void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const { // Save FPW into the appropriate stack slot... BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) - .addReg(MSP430::FPW, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); + .addReg(MSP430::FPW, RegState::Kill); // Update FPW with the new base value... BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW) diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index e5876e4019f..2ccbe898fa3 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -197,7 +197,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Opc = Mips::SDC1; } - BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill) + BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) .addImm(0).addFrameIndex(FI); } @@ -217,7 +217,7 @@ void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); NewMIs.push_back(MIB); @@ -285,13 +285,13 @@ foldMemoryOperandImpl(MachineFunction &MF, unsigned SrcReg = MI->getOperand(2).getReg(); bool isKill = MI->getOperand(2).isKill(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addImm(0).addFrameIndex(FI); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW)) - .addReg(DstReg, true, false, false, isDead) + .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) .addImm(0).addFrameIndex(FI); } } @@ -315,13 +315,13 @@ foldMemoryOperandImpl(MachineFunction &MF, unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addImm(0).addFrameIndex(FI) ; } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc)) - .addReg(DstReg, true, false, false, isDead) + .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) .addImm(0).addFrameIndex(FI); } } diff --git a/lib/Target/PIC16/PIC16InstrInfo.cpp b/lib/Target/PIC16/PIC16InstrInfo.cpp index c8cab3407d7..2a769e8ad16 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.cpp +++ b/lib/Target/PIC16/PIC16InstrInfo.cpp @@ -83,7 +83,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, //MachineFunction &MF = *MBB.getParent(); //MachineRegisterInfo &RI = MF.getRegInfo(); BuildMI(MBB, I, DL, get(PIC16::movwf)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addImm(PTLI->GetTmpOffsetForFI(FI, 1)) .addExternalSymbol(tmpName) .addImm(1); // Emit banksel for it. @@ -98,7 +98,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, unsigned opcode = (SrcReg == PIC16::FSR0) ? PIC16::save_fsr0 : PIC16::save_fsr1; BuildMI(MBB, I, DL, get(opcode)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addImm(PTLI->GetTmpOffsetForFI(FI, 3)) .addExternalSymbol(tmpName) .addImm(1); // Emit banksel for it. diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 81ff6c05079..778f0349d10 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -175,9 +175,9 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); bool Reg0IsDead = MI->getOperand(0).isDead(); return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) - .addReg(Reg0, true, false, false, Reg0IsDead) - .addReg(Reg2, false, false, Reg2IsKill) - .addReg(Reg1, false, false, Reg1IsKill) + .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) + .addReg(Reg2, getKillRegState(Reg2IsKill)) + .addReg(Reg1, getKillRegState(Reg1IsKill)) .addImm((ME+1) & 31) .addImm((MB-1) & 31); } @@ -370,7 +370,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, if (RC == PPC::GPRCRegisterClass) { if (SrcReg != PPC::LR) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) - .addReg(SrcReg, false, false, isKill), + .addReg(SrcReg, + getKillRegState(isKill)), FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, @@ -378,33 +379,43 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, // a hack. NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) - .addReg(PPC::R11, false, false, isKill), + .addReg(PPC::R11, + getKillRegState(isKill)), FrameIdx)); } } else if (RC == PPC::G8RCRegisterClass) { if (SrcReg != PPC::LR8) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) - .addReg(SrcReg, false, false, isKill), FrameIdx)); + .addReg(SrcReg, + getKillRegState(isKill)), + FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, // we use R11, which we know cannot be used in the prolog/epilog. This is // a hack. NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) - .addReg(PPC::X11, false, false, isKill), FrameIdx)); + .addReg(PPC::X11, + getKillRegState(isKill)), + FrameIdx)); } } else if (RC == PPC::F8RCRegisterClass) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) - .addReg(SrcReg, false, false, isKill), FrameIdx)); + .addReg(SrcReg, + getKillRegState(isKill)), + FrameIdx)); } else if (RC == PPC::F4RCRegisterClass) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) - .addReg(SrcReg, false, false, isKill), FrameIdx)); + .addReg(SrcReg, + getKillRegState(isKill)), + FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { // FIXME (64-bit): Enable NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) - .addReg(SrcReg, false, false, isKill), + .addReg(SrcReg, + getKillRegState(isKill)), FrameIdx)); return true; } else { @@ -423,7 +434,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, } NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) - .addReg(PPC::R0, false, false, isKill), + .addReg(PPC::R0, + getKillRegState(isKill)), FrameIdx)); } } else if (RC == PPC::CRBITRCRegisterClass) { @@ -461,7 +473,9 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), FrameIdx, 0, 0)); NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) - .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); + .addReg(SrcReg, getKillRegState(isKill)) + .addReg(PPC::R0) + .addReg(PPC::R0)); } else { assert(0 && "Unknown regclass!"); abort(); @@ -519,7 +533,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, abort(); } MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); NewMIs.push_back(MIB); @@ -678,13 +692,15 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW)) - .addReg(InReg, false, false, isKill), + .addReg(InReg, getKillRegState(isKill)), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ)) - .addReg(OutReg, true, false, false, isDead), + .addReg(OutReg, + RegState::Define | + getDeadRegState(isDead)), FrameIndex); } } else if ((Opc == PPC::OR8 && @@ -693,13 +709,15 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD)) - .addReg(InReg, false, false, isKill), + .addReg(InReg, getKillRegState(isKill)), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD)) - .addReg(OutReg, true, false, false, isDead), + .addReg(OutReg, + RegState::Define | + getDeadRegState(isDead)), FrameIndex); } } else if (Opc == PPC::FMRD) { @@ -707,13 +725,15 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD)) - .addReg(InReg, false, false, isKill), + .addReg(InReg, getKillRegState(isKill)), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD)) - .addReg(OutReg, true, false, false, isDead), + .addReg(OutReg, + RegState::Define | + getDeadRegState(isDead)), FrameIndex); } } else if (Opc == PPC::FMRS) { @@ -721,13 +741,15 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS)) - .addReg(InReg, false, false, isKill), + .addReg(InReg, getKillRegState(isKill)), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS)) - .addReg(OutReg, true, false, false, isDead), + .addReg(OutReg, + RegState::Define | + getDeadRegState(isDead)), FrameIndex); } } diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 657fc29bc6f..5d5beebda70 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -437,7 +437,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) .addImm(CalleeAmt >> 16); BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) - .addReg(TmpReg, false, false, true) + .addReg(TmpReg, RegState::Kill) .addImm(CalleeAmt & 0xFFFF); BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) .addReg(StackReg) @@ -537,12 +537,12 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, if (LP64) { if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) - .addReg(Reg, false, false, true) + .addReg(Reg, RegState::Kill) .addReg(PPC::X1) .addReg(MI.getOperand(1).getReg()); else BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) - .addReg(PPC::X0, false, false, true) + .addReg(PPC::X0, RegState::Kill) .addReg(PPC::X1) .addReg(MI.getOperand(1).getReg()); @@ -555,10 +555,10 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) .addReg(PPC::X1) .addImm(maxCallFrameSize) - .addReg(MI.getOperand(1).getReg(), false, true, true); + .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); } else { BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) - .addReg(Reg, false, false, true) + .addReg(Reg, RegState::Kill) .addReg(PPC::R1) .addReg(MI.getOperand(1).getReg()); @@ -571,7 +571,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) .addReg(PPC::R1) .addImm(maxCallFrameSize) - .addReg(MI.getOperand(1).getReg(), false, true, true); + .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); } // Discard the DYNALLOC instruction. @@ -607,7 +607,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, else // Implicitly kill the CR register. BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg) - .addReg(MI.getOperand(0).getReg(), false, true, true); + .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill); // If the saved register wasn't CR0, shift the bits left so that they are in // CR0's slot. @@ -615,13 +615,13 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, if (SrcReg != PPC::CR0) // rlwinm rA, rA, ShiftBits, 0, 31. BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) - .addReg(Reg, false, false, true) + .addReg(Reg, RegState::Kill) .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) .addImm(0) .addImm(31); addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) - .addReg(Reg, false, false, MI.getOperand(1).getImm()), + .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), FrameIndex); // Discard the pseudo instruction. @@ -735,7 +735,7 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) .addImm(Offset >> 16); BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) - .addReg(SReg, false, false, true) + .addReg(SReg, RegState::Kill) .addImm(Offset); // Convert into indexed form of the instruction: @@ -861,7 +861,7 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { .addImm(UsedRegMask); else BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) - .addReg(SrcReg, false, false, true) + .addReg(SrcReg, RegState::Kill) .addImm(UsedRegMask); } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { if (DstReg != SrcReg) @@ -870,7 +870,7 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { .addImm(UsedRegMask >> 16); else BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg, false, false, true) + .addReg(SrcReg, RegState::Kill) .addImm(UsedRegMask >> 16); } else { if (DstReg != SrcReg) @@ -879,11 +879,11 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { .addImm(UsedRegMask >> 16); else BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg, false, false, true) + .addReg(SrcReg, RegState::Kill) .addImm(UsedRegMask >> 16); BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) - .addReg(DstReg, false, false, true) + .addReg(DstReg, RegState::Kill) .addImm(UsedRegMask & 0xFFFF); } @@ -1101,7 +1101,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { .addImm(32 - Log2_32(MaxAlign)) .addImm(31); BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) - .addReg(PPC::R0, false, false, true) + .addReg(PPC::R0, RegState::Kill) .addImm(NegFrameSize); BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) .addReg(PPC::R1) @@ -1116,7 +1116,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) .addImm(NegFrameSize >> 16); BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) - .addReg(PPC::R0, false, false, true) + .addReg(PPC::R0, RegState::Kill) .addImm(NegFrameSize & 0xFFFF); BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) .addReg(PPC::R1) @@ -1148,7 +1148,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) .addImm(NegFrameSize >> 16); BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) - .addReg(PPC::X0, false, false, true) + .addReg(PPC::X0, RegState::Kill) .addImm(NegFrameSize & 0xFFFF); BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) .addReg(PPC::X1) @@ -1288,7 +1288,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) .addImm(FrameSize >> 16); BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) - .addReg(PPC::R0, false, false, true) + .addReg(PPC::R0, RegState::Kill) .addImm(FrameSize & 0xFFFF); BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) .addReg(PPC::R1) @@ -1312,7 +1312,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) .addImm(FrameSize >> 16); BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) - .addReg(PPC::X0, false, false, true) + .addReg(PPC::X0, RegState::Kill) .addImm(FrameSize & 0xFFFF); BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) .addReg(PPC::X1) @@ -1374,7 +1374,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) .addImm(CallerAllocatedAmt >> 16); BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) - .addReg(TmpReg, false, false, true) + .addReg(TmpReg, RegState::Kill) .addImm(CallerAllocatedAmt & 0xFFFF); BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) .addReg(StackReg) diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 7c230ec3a8b..d2f6b9bdcb3 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -152,13 +152,13 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, // On the order of operands here: think "[FrameIdx + 0] = SrcReg". if (RC == SP::IntRegsRegisterClass) BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); else if (RC == SP::FPRegsRegisterClass) BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); else if (RC == SP::DFPRegsRegisterClass) BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); else assert(0 && "Can't store this register to stack slot"); } @@ -181,7 +181,7 @@ void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); - MIB.addReg(SrcReg, false, false, isKill); + MIB.addReg(SrcReg, getKillRegState(isKill)); NewMIs.push_back(MIB); return; } @@ -260,13 +260,13 @@ MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, get(isFloat ? SP::STFri : SP::STDFri)) .addFrameIndex(FI) .addImm(0) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(isFloat ? SP::LDFri : SP::LDDFri)) - .addReg(DstReg, true, false, false, isDead) + .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) .addFrameIndex(FI) .addImm(0); } diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h index aa3e0333daf..39504cd44ce 100644 --- a/lib/Target/X86/X86InstrBuilder.h +++ b/lib/Target/X86/X86InstrBuilder.h @@ -83,13 +83,13 @@ inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB, inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset) { - return addOffset(MIB.addReg(Reg, false, false, isKill), Offset); + return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); } inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset) { - return addLeaOffset(MIB.addReg(Reg, false, false, isKill), Offset); + return addLeaOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); } /// addRegReg - This function is used to add a memory reference of the form: @@ -97,8 +97,8 @@ inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) { - return MIB.addReg(Reg1, false, false, isKill1).addImm(1) - .addReg(Reg2, false, false, isKill2).addImm(0); + return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) + .addReg(Reg2, getKillRegState(isKill2)).addImm(0); } inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB, diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 85756a1cdcd..5fca9c71c9d 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1032,8 +1032,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned A = MI->getOperand(0).getReg(); unsigned M = MI->getOperand(3).getImm(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) - .addReg(A, true, false, false, isDead) - .addReg(B, false, false, isKill).addImm(M); + .addReg(A, RegState::Define | getDeadRegState(isDead)) + .addReg(B, getKillRegState(isKill)).addImm(M); break; } case X86::SHL64ri: { @@ -1044,8 +1044,10 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, if (ShAmt == 0 || ShAmt >= 4) return 0; NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) - .addReg(Dest, true, false, false, isDead) - .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0); + .addReg(Dest, RegState::Define | getDeadRegState(isDead)) + .addReg(0).addImm(1 << ShAmt) + .addReg(Src, getKillRegState(isKill)) + .addImm(0); break; } case X86::SHL32ri: { @@ -1058,9 +1060,9 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned Opc = TM.getSubtarget().is64Bit() ? X86::LEA64_32r : X86::LEA32r; NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(Dest, true, false, false, isDead) + .addReg(Dest, RegState::Define | getDeadRegState(isDead)) .addReg(0).addImm(1 << ShAmt) - .addReg(Src, false, false, isKill).addImm(0); + .addReg(Src, getKillRegState(isKill)).addImm(0); break; } case X86::SHL16ri: { @@ -1083,17 +1085,20 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); MachineInstr *InsMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg) - .addReg(leaInReg).addReg(Src, false, false, isKill) + .addReg(leaInReg) + .addReg(Src, getKillRegState(isKill)) .addImm(X86::SUBREG_16BIT); NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg) .addReg(0).addImm(1 << ShAmt) - .addReg(leaInReg, false, false, true).addImm(0); + .addReg(leaInReg, RegState::Kill) + .addImm(0); MachineInstr *ExtMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG)) - .addReg(Dest, true, false, false, isDead) - .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT); + .addReg(Dest, RegState::Define | getDeadRegState(isDead)) + .addReg(leaOutReg, RegState::Kill) + .addImm(X86::SUBREG_16BIT); if (LV) { // Update live variables @@ -1107,9 +1112,10 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, return ExtMI; } else { NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) - .addReg(Dest, true, false, false, isDead) + .addReg(Dest, RegState::Define | getDeadRegState(isDead)) .addReg(0).addImm(1 << ShAmt) - .addReg(Src, false, false, isKill).addImm(0); + .addReg(Src, getKillRegState(isKill)) + .addImm(0); } break; } @@ -1130,7 +1136,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r : (is64Bit ? X86::LEA64_32r : X86::LEA32r); NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(Dest, true, false, false, isDead), + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), Src, isKill, 1); break; } @@ -1139,7 +1146,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, if (DisableLEA16) return 0; assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) - .addReg(Dest, true, false, false, isDead), + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), Src, isKill, 1); break; case X86::DEC64r: @@ -1149,7 +1157,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r : (is64Bit ? X86::LEA64_32r : X86::LEA32r); NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(Dest, true, false, false, isDead), + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), Src, isKill, -1); break; } @@ -1158,7 +1167,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, if (DisableLEA16) return 0; assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) - .addReg(Dest, true, false, false, isDead), + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), Src, isKill, -1); break; case X86::ADD64rr: @@ -1169,7 +1179,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned Src2 = MI->getOperand(2).getReg(); bool isKill2 = MI->getOperand(2).isKill(); NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(Dest, true, false, false, isDead), + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), Src, isKill, Src2, isKill2); if (LV && isKill2) LV->replaceKillInstruction(Src2, MI, NewMI); @@ -1181,7 +1192,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned Src2 = MI->getOperand(2).getReg(); bool isKill2 = MI->getOperand(2).isKill(); NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) - .addReg(Dest, true, false, false, isDead), + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), Src, isKill, Src2, isKill2); if (LV && isKill2) LV->replaceKillInstruction(Src2, MI, NewMI); @@ -1192,7 +1204,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImm()) NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) - .addReg(Dest, true, false, false, isDead), + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), Src, isKill, MI->getOperand(2).getImm()); break; case X86::ADD32ri: @@ -1201,7 +1214,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, if (MI->getOperand(2).isImm()) { unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(Dest, true, false, false, isDead), + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), Src, isKill, MI->getOperand(2).getImm()); } break; @@ -1211,7 +1225,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImm()) NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) - .addReg(Dest, true, false, false, isDead), + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), Src, isKill, MI->getOperand(2).getImm()); break; case X86::SHL16ri: @@ -1229,7 +1244,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, : (MIOpc == X86::SHL32ri ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r); NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(Dest, true, false, false, isDead), AM); + .addReg(Dest, RegState::Define | + getDeadRegState(isDead)), AM); if (isKill) NewMI->getOperand(3).setIsKill(true); } @@ -1870,7 +1886,7 @@ void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, DebugLoc DL = DebugLoc::getUnknownLoc(); if (MI != MBB.end()) DL = MI->getDebugLoc(); addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) - .addReg(SrcReg, false, false, isKill); + .addReg(SrcReg, getKillRegState(isKill)); } void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -1885,7 +1901,7 @@ void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB.addOperand(Addr[i]); - MIB.addReg(SrcReg, false, false, isKill); + MIB.addReg(SrcReg, getKillRegState(isKill)); NewMIs.push_back(MIB); } @@ -2001,7 +2017,7 @@ bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, // Add the callee-saved register as live-in. It's killed at the spill. MBB.addLiveIn(Reg); BuildMI(MBB, MI, DL, get(Opc)) - .addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); + .addReg(Reg, RegState::Kill); } return true; } @@ -2396,7 +2412,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, MachineInstrBuilder MIB(DataMI); if (FoldedStore) - MIB.addReg(Reg, true); + MIB.addReg(Reg, RegState::Define); for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) MIB.addOperand(BeforeOps[i]); if (FoldedLoad) @@ -2405,7 +2421,11 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, MIB.addOperand(AfterOps[i]); for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { MachineOperand &MO = ImpOps[i]; - MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead()); + MIB.addReg(MO.getReg(), + getDefRegState(MO.isDef()) | + RegState::Implicit | + getKillRegState(MO.isKill()) | + getDeadRegState(MO.isDead())); } // Change CMP32ri r, 0 back to TEST32rr r, r, etc. unsigned NewOpc = 0; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 6b0df225fb7..5af1fb17818 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -789,7 +789,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { // Save EBP into the appropriate stack slot... BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) - .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); + .addReg(FramePtr, RegState::Kill); if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. @@ -860,7 +860,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { } else { // Save EAX BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) - .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); + .addReg(X86::EAX, RegState::Kill); // Allocate NumBytes-4 bytes on stack. We'll also use 4 already // allocated bytes for EAX. BuildMI(MBB, MBBI, DL, diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index e328b460f05..0402f59aa5d 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -397,7 +397,7 @@ void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, DebugLoc DL = DebugLoc::getUnknownLoc(); if (I != MBB.end()) DL = I->getDebugLoc(); BuildMI(MBB, I, DL, get(XCore::STWFI)) - .addReg(SrcReg, false, false, isKill) + .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIndex) .addImm(0); } diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index ef5f9f99acc..82cd92d5685 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -237,18 +237,18 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, case XCore::LDWFI: New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) .addReg(FramePtr) - .addReg(ScratchReg, false, false, true); + .addReg(ScratchReg, RegState::Kill); break; case XCore::STWFI: New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) - .addReg(Reg, false, false, isKill) + .addReg(Reg, getKillRegState(isKill)) .addReg(FramePtr) - .addReg(ScratchReg, false, false, true); + .addReg(ScratchReg, RegState::Kill); break; case XCore::LDAWFI: New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) .addReg(FramePtr) - .addReg(ScratchReg, false, false, true); + .addReg(ScratchReg, RegState::Kill); break; default: assert(0 && "Unexpected Opcode\n"); @@ -262,7 +262,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; case XCore::STWFI: New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) - .addReg(Reg, false, false, isKill) + .addReg(Reg, getKillRegState(isKill)) .addReg(FramePtr) .addImm(Offset); break; @@ -293,7 +293,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, case XCore::STWFI: NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; BuildMI(MBB, II, dl, TII.get(NewOpcode)) - .addReg(Reg, false, false, isKill) + .addReg(Reg, getKillRegState(isKill)) .addImm(Offset); break; case XCore::LDAWFI: