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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-19 02:25:01 +00:00
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -155,7 +155,10 @@ public:
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/// return a new machine instruction. If an instruction cannot commute, it
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/// return a new machine instruction. If an instruction cannot commute, it
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/// can also return null.
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/// can also return null.
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///
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///
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virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
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/// If NewMI is true, then a new machine instruction must be created.
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///
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virtual MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI = false) const = 0;
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/// CommuteChangesDestination - Return true if commuting the specified
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/// CommuteChangesDestination - Return true if commuting the specified
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/// instruction will also changes the destination operand. Also return the
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/// instruction will also changes the destination operand. Also return the
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@@ -411,7 +414,8 @@ protected:
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TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
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TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
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: TargetInstrInfo(desc, NumOpcodes) {}
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: TargetInstrInfo(desc, NumOpcodes) {}
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public:
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public:
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virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
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virtual MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI = false) const;
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virtual bool CommuteChangesDestination(MachineInstr *MI,
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virtual bool CommuteChangesDestination(MachineInstr *MI,
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unsigned &OpIdx) const;
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unsigned &OpIdx) const;
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virtual bool PredicateInstruction(MachineInstr *MI,
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virtual bool PredicateInstruction(MachineInstr *MI,
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@@ -14,24 +14,39 @@
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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using namespace llvm;
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// commuteInstruction - The default implementation of this method just exchanges
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// commuteInstruction - The default implementation of this method just exchanges
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// operand 1 and 2.
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// operand 1 and 2.
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MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
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MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
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assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
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"This only knows how to commute register operands so far");
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"This only knows how to commute register operands so far");
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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bool ChangeReg0 = false;
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if (MI->getOperand(0).getReg() == Reg1) {
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if (MI->getOperand(0).getReg() == Reg1) {
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// Must be two address instruction!
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// Must be two address instruction!
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assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
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assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
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"Expecting a two-address instruction!");
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"Expecting a two-address instruction!");
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Reg2IsKill = false;
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Reg2IsKill = false;
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MI->getOperand(0).setReg(Reg2);
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ChangeReg0 = true;
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}
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}
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if (NewMI) {
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// Create a new instruction.
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unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
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bool Reg0IsDead = MI->getOperand(0).isDead();
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return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead)
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.addReg(Reg2, false, false, Reg2IsKill)
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.addReg(Reg1, false, false, Reg1IsKill);
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}
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if (ChangeReg0)
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MI->getOperand(0).setReg(Reg2);
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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MI->getOperand(1).setReg(Reg2);
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MI->getOperand(2).setIsKill(Reg1IsKill);
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MI->getOperand(2).setIsKill(Reg1IsKill);
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@@ -136,10 +136,11 @@ unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// rotate amt is zero. We also have to munge the immediates a bit.
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// rotate amt is zero. We also have to munge the immediates a bit.
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MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
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MachineInstr *
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PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
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// Normal instructions can be commuted the obvious way.
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// Normal instructions can be commuted the obvious way.
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if (MI->getOpcode() != PPC::RLWIMI)
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if (MI->getOpcode() != PPC::RLWIMI)
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return TargetInstrInfoImpl::commuteInstruction(MI);
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return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
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// Cannot commute if it has a non-zero rotate count.
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// Cannot commute if it has a non-zero rotate count.
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if (MI->getOperand(3).getImm() != 0)
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if (MI->getOperand(3).getImm() != 0)
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@@ -158,23 +159,40 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
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unsigned Reg2 = MI->getOperand(2).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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bool ChangeReg0 = false;
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// If machine instrs are no longer in two-address forms, update
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// If machine instrs are no longer in two-address forms, update
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// destination register as well.
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// destination register as well.
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if (Reg0 == Reg1) {
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if (Reg0 == Reg1) {
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// Must be two address instruction!
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// Must be two address instruction!
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assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
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assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
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"Expecting a two-address instruction!");
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"Expecting a two-address instruction!");
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MI->getOperand(0).setReg(Reg2);
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Reg2IsKill = false;
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Reg2IsKill = false;
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ChangeReg0 = true;
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}
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}
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// Masks.
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unsigned MB = MI->getOperand(4).getImm();
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unsigned ME = MI->getOperand(5).getImm();
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if (NewMI) {
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// Create a new instruction.
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unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
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bool Reg0IsDead = MI->getOperand(0).isDead();
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return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead)
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.addReg(Reg2, false, false, Reg2IsKill)
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.addReg(Reg1, false, false, Reg1IsKill)
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.addImm((ME+1) & 31)
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.addImm((MB-1) & 31);
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}
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if (ChangeReg0)
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MI->getOperand(0).setReg(Reg2);
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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MI->getOperand(1).setReg(Reg2);
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MI->getOperand(2).setIsKill(Reg1IsKill);
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MI->getOperand(2).setIsKill(Reg1IsKill);
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MI->getOperand(1).setIsKill(Reg2IsKill);
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MI->getOperand(1).setIsKill(Reg2IsKill);
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// Swap the mask around.
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// Swap the mask around.
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unsigned MB = MI->getOperand(4).getImm();
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unsigned ME = MI->getOperand(5).getImm();
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MI->getOperand(4).setImm((ME+1) & 31);
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MI->getOperand(4).setImm((ME+1) & 31);
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MI->getOperand(5).setImm((MB-1) & 31);
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MI->getOperand(5).setImm((MB-1) & 31);
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return MI;
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return MI;
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@@ -96,7 +96,7 @@ public:
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// rotate amt is zero. We also have to munge the immediates a bit.
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// rotate amt is zero. We also have to munge the immediates a bit.
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virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
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virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
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virtual void insertNoop(MachineBasicBlock &MBB,
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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MachineBasicBlock::iterator MI) const;
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@@ -1146,7 +1146,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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/// commute them.
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///
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///
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MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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MachineInstr *
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X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
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switch (MI->getOpcode()) {
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switch (MI->getOpcode()) {
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case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
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case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
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case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
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case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
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@@ -1276,7 +1277,7 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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// Fallthrough intended.
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// Fallthrough intended.
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}
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}
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default:
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default:
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return TargetInstrInfoImpl::commuteInstruction(MI);
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return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
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}
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}
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}
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}
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@@ -283,7 +283,7 @@ public:
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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/// commute them.
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///
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///
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virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
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virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
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// Branch analysis.
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// Branch analysis.
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virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
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virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
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