Add option to commuteInstruction() which forces it to create a new (commuted) instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2008-06-16 07:33:11 +00:00
parent 3557801289
commit 58dcb0e0cd
6 changed files with 51 additions and 13 deletions

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@@ -155,7 +155,10 @@ public:
/// return a new machine instruction. If an instruction cannot commute, it /// return a new machine instruction. If an instruction cannot commute, it
/// can also return null. /// can also return null.
/// ///
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0; /// If NewMI is true, then a new machine instruction must be created.
///
virtual MachineInstr *commuteInstruction(MachineInstr *MI,
bool NewMI = false) const = 0;
/// CommuteChangesDestination - Return true if commuting the specified /// CommuteChangesDestination - Return true if commuting the specified
/// instruction will also changes the destination operand. Also return the /// instruction will also changes the destination operand. Also return the
@@ -411,7 +414,8 @@ protected:
TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
: TargetInstrInfo(desc, NumOpcodes) {} : TargetInstrInfo(desc, NumOpcodes) {}
public: public:
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; virtual MachineInstr *commuteInstruction(MachineInstr *MI,
bool NewMI = false) const;
virtual bool CommuteChangesDestination(MachineInstr *MI, virtual bool CommuteChangesDestination(MachineInstr *MI,
unsigned &OpIdx) const; unsigned &OpIdx) const;
virtual bool PredicateInstruction(MachineInstr *MI, virtual bool PredicateInstruction(MachineInstr *MI,

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@@ -14,24 +14,39 @@
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
using namespace llvm; using namespace llvm;
// commuteInstruction - The default implementation of this method just exchanges // commuteInstruction - The default implementation of this method just exchanges
// operand 1 and 2. // operand 1 and 2.
MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const { MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
bool NewMI) const {
assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
"This only knows how to commute register operands so far"); "This only knows how to commute register operands so far");
unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg1 = MI->getOperand(1).getReg();
unsigned Reg2 = MI->getOperand(2).getReg(); unsigned Reg2 = MI->getOperand(2).getReg();
bool Reg1IsKill = MI->getOperand(1).isKill(); bool Reg1IsKill = MI->getOperand(1).isKill();
bool Reg2IsKill = MI->getOperand(2).isKill(); bool Reg2IsKill = MI->getOperand(2).isKill();
bool ChangeReg0 = false;
if (MI->getOperand(0).getReg() == Reg1) { if (MI->getOperand(0).getReg() == Reg1) {
// Must be two address instruction! // Must be two address instruction!
assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
"Expecting a two-address instruction!"); "Expecting a two-address instruction!");
Reg2IsKill = false; Reg2IsKill = false;
MI->getOperand(0).setReg(Reg2); ChangeReg0 = true;
} }
if (NewMI) {
// Create a new instruction.
unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
bool Reg0IsDead = MI->getOperand(0).isDead();
return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead)
.addReg(Reg2, false, false, Reg2IsKill)
.addReg(Reg1, false, false, Reg1IsKill);
}
if (ChangeReg0)
MI->getOperand(0).setReg(Reg2);
MI->getOperand(2).setReg(Reg1); MI->getOperand(2).setReg(Reg1);
MI->getOperand(1).setReg(Reg2); MI->getOperand(1).setReg(Reg2);
MI->getOperand(2).setIsKill(Reg1IsKill); MI->getOperand(2).setIsKill(Reg1IsKill);

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@@ -136,10 +136,11 @@ unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
// commuteInstruction - We can commute rlwimi instructions, but only if the // commuteInstruction - We can commute rlwimi instructions, but only if the
// rotate amt is zero. We also have to munge the immediates a bit. // rotate amt is zero. We also have to munge the immediates a bit.
MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { MachineInstr *
PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
// Normal instructions can be commuted the obvious way. // Normal instructions can be commuted the obvious way.
if (MI->getOpcode() != PPC::RLWIMI) if (MI->getOpcode() != PPC::RLWIMI)
return TargetInstrInfoImpl::commuteInstruction(MI); return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
// Cannot commute if it has a non-zero rotate count. // Cannot commute if it has a non-zero rotate count.
if (MI->getOperand(3).getImm() != 0) if (MI->getOperand(3).getImm() != 0)
@@ -158,23 +159,40 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
unsigned Reg2 = MI->getOperand(2).getReg(); unsigned Reg2 = MI->getOperand(2).getReg();
bool Reg1IsKill = MI->getOperand(1).isKill(); bool Reg1IsKill = MI->getOperand(1).isKill();
bool Reg2IsKill = MI->getOperand(2).isKill(); bool Reg2IsKill = MI->getOperand(2).isKill();
bool ChangeReg0 = false;
// If machine instrs are no longer in two-address forms, update // If machine instrs are no longer in two-address forms, update
// destination register as well. // destination register as well.
if (Reg0 == Reg1) { if (Reg0 == Reg1) {
// Must be two address instruction! // Must be two address instruction!
assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
"Expecting a two-address instruction!"); "Expecting a two-address instruction!");
MI->getOperand(0).setReg(Reg2);
Reg2IsKill = false; Reg2IsKill = false;
ChangeReg0 = true;
} }
// Masks.
unsigned MB = MI->getOperand(4).getImm();
unsigned ME = MI->getOperand(5).getImm();
if (NewMI) {
// Create a new instruction.
unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
bool Reg0IsDead = MI->getOperand(0).isDead();
return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead)
.addReg(Reg2, false, false, Reg2IsKill)
.addReg(Reg1, false, false, Reg1IsKill)
.addImm((ME+1) & 31)
.addImm((MB-1) & 31);
}
if (ChangeReg0)
MI->getOperand(0).setReg(Reg2);
MI->getOperand(2).setReg(Reg1); MI->getOperand(2).setReg(Reg1);
MI->getOperand(1).setReg(Reg2); MI->getOperand(1).setReg(Reg2);
MI->getOperand(2).setIsKill(Reg1IsKill); MI->getOperand(2).setIsKill(Reg1IsKill);
MI->getOperand(1).setIsKill(Reg2IsKill); MI->getOperand(1).setIsKill(Reg2IsKill);
// Swap the mask around. // Swap the mask around.
unsigned MB = MI->getOperand(4).getImm();
unsigned ME = MI->getOperand(5).getImm();
MI->getOperand(4).setImm((ME+1) & 31); MI->getOperand(4).setImm((ME+1) & 31);
MI->getOperand(5).setImm((MB-1) & 31); MI->getOperand(5).setImm((MB-1) & 31);
return MI; return MI;

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@@ -96,7 +96,7 @@ public:
// commuteInstruction - We can commute rlwimi instructions, but only if the // commuteInstruction - We can commute rlwimi instructions, but only if the
// rotate amt is zero. We also have to munge the immediates a bit. // rotate amt is zero. We also have to munge the immediates a bit.
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
virtual void insertNoop(MachineBasicBlock &MBB, virtual void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const; MachineBasicBlock::iterator MI) const;

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@@ -1146,7 +1146,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
/// commuteInstruction - We have a few instructions that must be hacked on to /// commuteInstruction - We have a few instructions that must be hacked on to
/// commute them. /// commute them.
/// ///
MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { MachineInstr *
X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
@@ -1276,7 +1277,7 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
// Fallthrough intended. // Fallthrough intended.
} }
default: default:
return TargetInstrInfoImpl::commuteInstruction(MI); return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
} }
} }

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@@ -283,7 +283,7 @@ public:
/// commuteInstruction - We have a few instructions that must be hacked on to /// commuteInstruction - We have a few instructions that must be hacked on to
/// commute them. /// commute them.
/// ///
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
// Branch analysis. // Branch analysis.
virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;