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https://github.com/c64scene-ar/llvm-6502.git
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Fix frame index code to generate legal PowerPC instructions. About half of
Shootout now works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20940 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -612,9 +612,8 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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}
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}
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if(Address.getOpcode() == ISD::FrameIndex) {
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if(Address.getOpcode() == ISD::FrameIndex) {
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BuildMI(BB, Opc, 2, Result)
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Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
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.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
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addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
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.addReg(PPC::R1);
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} else {
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} else {
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int offset;
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int offset;
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SelectAddr(Address, Tmp1, offset);
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SelectAddr(Address, Tmp1, offset);
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@ -730,7 +729,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::FrameIndex:
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case ISD::FrameIndex:
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Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
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Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
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addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1);
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addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
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return Result;
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return Result;
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case ISD::GlobalAddress: {
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case ISD::GlobalAddress: {
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@ -782,9 +781,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Tmp3 = 0; // Silence GCC warning.
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Tmp3 = 0; // Silence GCC warning.
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}
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}
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if(Address.getOpcode() == ISD::FrameIndex) {
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if(Address.getOpcode() == ISD::FrameIndex) {
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BuildMI(BB, Opc, 2, Result)
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Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
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.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
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addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
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.addReg(PPC::R1);
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} else {
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} else {
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int offset;
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int offset;
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SelectAddr(Address, Tmp1, offset);
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SelectAddr(Address, Tmp1, offset);
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@ -1343,8 +1341,8 @@ void ISel::Select(SDOperand N) {
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}
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}
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else if(Address.getOpcode() == ISD::FrameIndex)
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else if(Address.getOpcode() == ISD::FrameIndex)
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{
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{
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BuildMI(BB, Opc, 2).addReg(Tmp1)
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Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
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.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex());
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addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2);
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}
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}
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else
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else
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{
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{
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