6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-19 03:29:22 +00:00
Code Issues Projects Releases Wiki Activity

Fix frame index code to generate legal PowerPC instructions. About half of

Browse Source 
Shootout now works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20940 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-03-30 02:23:08 +00:00
parent 01d05266f9
commit 58f718cd97
1 changed files with 7 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -612,9 +612,8 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
}
if(Address.getOpcode() == ISD::FrameIndex) {
BuildMI(BB, Opc, 2, Result)
.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
.addReg(PPC::R1);
Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
} else {
int offset;
SelectAddr(Address, Tmp1, offset);
@ -730,7 +729,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
case ISD::FrameIndex:
Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1);
addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
return Result;
case ISD::GlobalAddress: {
@ -782,9 +781,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
Tmp3 = 0; // Silence GCC warning.
}
if(Address.getOpcode() == ISD::FrameIndex) {
BuildMI(BB, Opc, 2, Result)
.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
.addReg(PPC::R1);
Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
} else {
int offset;
SelectAddr(Address, Tmp1, offset);
@ -1343,8 +1341,8 @@ void ISel::Select(SDOperand N) {
}
else if(Address.getOpcode() == ISD::FrameIndex)
{
BuildMI(BB, Opc, 2).addReg(Tmp1)
.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex());
Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2);
}
else
{