6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 18:29:45 +00:00
Code Issues Projects Releases Wiki Activity

Do not extend extension results beyond the use of a PHI instruction at the start of a use block. A PHI use is expected to kill its source values.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93895 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-01-19 19:45:51 +00:00
parent 91093ecf0f
commit 590d16be6f
2 changed files with 69 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/CodeGen/OptimizeExts.cpp
View File

@ -143,11 +143,23 @@ bool OptimizeExts::OptimizeInstr(MachineInstr *MI, MachineBasicBlock *MBB,
// Now replace all uses.
if (!Uses.empty()) {
SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
// Look for PHI uses of the extended result, we don't want to extend the
// liveness of a PHI input. It breaks all kinds of assumptions down
// stream. A PHI use is expected to be the kill of its source values.
UI = MRI->use_begin(DstReg);
for (MachineRegisterInfo::use_iterator UE = MRI->use_end(); UI != UE;
++UI)
if (UI->getOpcode() == TargetInstrInfo::PHI)
PHIBBs.insert(UI->getParent());
const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
MachineOperand *UseMO = Uses[i];
MachineInstr *UseMI = UseMO->getParent();
MachineBasicBlock *UseMBB = UseMI->getParent();
if (PHIBBs.count(UseMBB))
continue;
unsigned NewVR = MRI->createVirtualRegister(RC);
BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
TII->get(TargetInstrInfo::EXTRACT_SUBREG), NewVR)

57
test/CodeGen/X86/2010-01-19-OptExtBug.ll Normal file
View File

@ -0,0 +1,57 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -relocation-model=pic -disable-fp-elim -stats |& not grep ext-opt
define fastcc i8* @S_scan_str(i8* %start, i32 %keep_quoted, i32 %keep_delims) nounwind ssp {
entry:
switch i8 undef, label %bb6 [
i8 9, label %bb5
i8 32, label %bb5
i8 10, label %bb5
i8 13, label %bb5
i8 12, label %bb5
]
bb5: ; preds = %entry, %entry, %entry, %entry, %entry
br label %bb6
bb6: ; preds = %bb5, %entry
br i1 undef, label %bb7, label %bb9
bb7: ; preds = %bb6
unreachable
bb9: ; preds = %bb6
%0 = load i8* undef, align 1 ; <i8> [#uses=3]
br i1 undef, label %bb12, label %bb10
bb10: ; preds = %bb9
br i1 undef, label %bb12, label %bb11
bb11: ; preds = %bb10
unreachable
bb12: ; preds = %bb10, %bb9
br i1 undef, label %bb13, label %bb14
bb13: ; preds = %bb12
store i8 %0, i8* undef, align 1
%1 = zext i8 %0 to i32 ; <i32> [#uses=1]
br label %bb18
bb14: ; preds = %bb12
br label %bb18
bb18: ; preds = %bb14, %bb13
%termcode.0 = phi i32 [ %1, %bb13 ], [ undef, %bb14 ] ; <i32> [#uses=2]
%2 = icmp eq i8 %0, 0 ; <i1> [#uses=1]
br i1 %2, label %bb21, label %bb19
bb19: ; preds = %bb18
br i1 undef, label %bb21, label %bb20
bb20: ; preds = %bb19
br label %bb21
bb21: ; preds = %bb20, %bb19, %bb18
%termcode.1 = phi i32 [ %termcode.0, %bb18 ], [ %termcode.0, %bb19 ], [ undef, %bb20 ] ; <i32> [#uses=0]
unreachable
}