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implement support for spliting and scalarizing vector setcc's. This

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finishes off enough support for vector compares to get the icmp/fcmp
version of 2008-07-23-VSetCC.ll passing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74961 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-07-07 22:47:46 +00:00
parent 9800e849c1
commit 5962ed0a36
3 changed files with 52 additions and 9 deletions
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3
lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -520,6 +520,7 @@ private:
SDValue ScalarizeVecRes_UNDEF(SDNode *N);
SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
SDValue ScalarizeVecRes_VSETCC(SDNode *N);
SDValue ScalarizeVecRes_SETCC(SDNode *N);
// Vector Operand Scalarization: <1 x ty> -> ty.
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
@ -560,7 +561,7 @@ private:
void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
SDValue &Hi);
void SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
bool SplitVectorOperand(SDNode *N, unsigned OpNo);

30
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -56,6 +56,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
case ISD::CTLZ:
case ISD::CTPOP:
@ -250,6 +251,14 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
return DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Res);
}
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
SDValue LHS = GetScalarizedVector(N->getOperand(0));
SDValue RHS = GetScalarizedVector(N->getOperand(1));
DebugLoc DL = N->getDebugLoc();
// Turn it into a scalar SETCC.
return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
}
//===----------------------------------------------------------------------===//
@ -381,10 +390,17 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
case ISD::LOAD:
SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
break;
case ISD::VECTOR_SHUFFLE:
SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); break;
case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
break;
case ISD::VSETCC:
case ISD::SETCC:
SplitVecRes_SETCC(N, Lo, Hi);
break;
case ISD::CTTZ:
case ISD::CTLZ:
@ -874,8 +890,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
}
}
void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
SDValue &Hi) {
void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
MVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
@ -884,11 +899,10 @@ void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
GetSplitVector(N->getOperand(0), LL, LH);
GetSplitVector(N->getOperand(1), RL, RH);
Lo = DAG.getNode(ISD::VSETCC, dl, LoVT, LL, RL, N->getOperand(2));
Hi = DAG.getNode(ISD::VSETCC, dl, HiVT, LH, RH, N->getOperand(2));
Lo = DAG.getNode(N->getOpcode(), dl, LoVT, LL, RL, N->getOperand(2));
Hi = DAG.getNode(N->getOpcode(), dl, HiVT, LH, RH, N->getOperand(2));
}
//===----------------------------------------------------------------------===//
// Operand Vector Splitting
//===----------------------------------------------------------------------===//

28
test/CodeGen/X86/2008-07-23-VSetCC.ll
View File

@ -27,4 +27,32 @@ bb.nph: ; preds = %bb.nph, %0
ret void
}
define void @entry2(i32 %m_task_id, i32 %start_x, i32 %end_x) nounwind {
br i1 false, label %bb.nph, label %._crit_edge
bb.nph: ; preds = %bb.nph, %0
%X = icmp sgt <4 x i32> zeroinitializer, < i32 -128, i32 -128, i32 -128, i32 -128 > ; <<4 x i32>>:1 [#uses=1]
sext <4 x i1> %X to <4 x i32>
extractelement <4 x i32> %1, i32 3 ; <i32>:2 [#uses=1]
lshr i32 %2, 31 ; <i32>:3 [#uses=1]
trunc i32 %3 to i1 ; <i1>:4 [#uses=1]
select i1 %4, i32 -1, i32 0 ; <i32>:5 [#uses=1]
insertelement <4 x i32> zeroinitializer, i32 %5, i32 3 ; <<4 x i32>>:6 [#uses=1]
and <4 x i32> zeroinitializer, %6 ; <<4 x i32>>:7 [#uses=1]
bitcast <4 x i32> %7 to <4 x float> ; <<4 x float>>:8 [#uses=1]
fmul <4 x float> zeroinitializer, %8 ; <<4 x float>>:9 [#uses=1]
bitcast <4 x float> %9 to <4 x i32> ; <<4 x i32>>:10 [#uses=1]
or <4 x i32> %10, zeroinitializer ; <<4 x i32>>:11 [#uses=1]
bitcast <4 x i32> %11 to <4 x float> ; <<4 x float>>:12 [#uses=1]
fmul <4 x float> %12, < float 1.000000e+02, float 1.000000e+02, float 1.000000e+02, float 1.000000e+02 > ; <<4 x float>>:13 [#uses=1]
fsub <4 x float> %13, < float 1.000000e+02, float 1.000000e+02, float 1.000000e+02, float 1.000000e+02 > ; <<4 x float>>:14 [#uses=1]
extractelement <4 x float> %14, i32 3 ; <float>:15 [#uses=1]
call float @fmaxf( float 0.000000e+00, float %15 ) ; <float>:16 [#uses=0]
br label %bb.nph
._crit_edge: ; preds = %0
ret void
}
declare float @fmaxf(float, float)