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https://github.com/c64scene-ar/llvm-6502.git
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implement support for spliting and scalarizing vector setcc's. This
finishes off enough support for vector compares to get the icmp/fcmp version of 2008-07-23-VSetCC.ll passing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74961 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -520,6 +520,7 @@ private:
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SDValue ScalarizeVecRes_UNDEF(SDNode *N);
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SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
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SDValue ScalarizeVecRes_VSETCC(SDNode *N);
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SDValue ScalarizeVecRes_SETCC(SDNode *N);
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// Vector Operand Scalarization: <1 x ty> -> ty.
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bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
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@ -560,7 +561,7 @@ private:
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void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
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SDValue &Hi);
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void SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
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// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
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bool SplitVectorOperand(SDNode *N, unsigned OpNo);
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@ -56,6 +56,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
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case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
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case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
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case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
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case ISD::CTLZ:
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case ISD::CTPOP:
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@ -250,6 +251,14 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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return DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Res);
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}
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(0));
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SDValue RHS = GetScalarizedVector(N->getOperand(1));
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DebugLoc DL = N->getDebugLoc();
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// Turn it into a scalar SETCC.
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return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
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}
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//===----------------------------------------------------------------------===//
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@ -381,10 +390,17 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
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case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
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case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
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case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
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case ISD::LOAD:
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SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
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break;
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case ISD::VECTOR_SHUFFLE:
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SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); break;
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case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
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SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
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break;
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case ISD::VSETCC:
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case ISD::SETCC:
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SplitVecRes_SETCC(N, Lo, Hi);
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break;
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case ISD::CTTZ:
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case ISD::CTLZ:
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@ -874,8 +890,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
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}
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}
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void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
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MVT LoVT, HiVT;
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DebugLoc dl = N->getDebugLoc();
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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@ -884,11 +899,10 @@ void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
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GetSplitVector(N->getOperand(0), LL, LH);
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GetSplitVector(N->getOperand(1), RL, RH);
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Lo = DAG.getNode(ISD::VSETCC, dl, LoVT, LL, RL, N->getOperand(2));
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Hi = DAG.getNode(ISD::VSETCC, dl, HiVT, LH, RH, N->getOperand(2));
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Lo = DAG.getNode(N->getOpcode(), dl, LoVT, LL, RL, N->getOperand(2));
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Hi = DAG.getNode(N->getOpcode(), dl, HiVT, LH, RH, N->getOperand(2));
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}
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//===----------------------------------------------------------------------===//
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// Operand Vector Splitting
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//===----------------------------------------------------------------------===//
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@ -27,4 +27,32 @@ bb.nph: ; preds = %bb.nph, %0
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ret void
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}
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define void @entry2(i32 %m_task_id, i32 %start_x, i32 %end_x) nounwind {
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br i1 false, label %bb.nph, label %._crit_edge
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bb.nph: ; preds = %bb.nph, %0
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%X = icmp sgt <4 x i32> zeroinitializer, < i32 -128, i32 -128, i32 -128, i32 -128 > ; <<4 x i32>>:1 [#uses=1]
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sext <4 x i1> %X to <4 x i32>
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extractelement <4 x i32> %1, i32 3 ; <i32>:2 [#uses=1]
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lshr i32 %2, 31 ; <i32>:3 [#uses=1]
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trunc i32 %3 to i1 ; <i1>:4 [#uses=1]
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select i1 %4, i32 -1, i32 0 ; <i32>:5 [#uses=1]
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insertelement <4 x i32> zeroinitializer, i32 %5, i32 3 ; <<4 x i32>>:6 [#uses=1]
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and <4 x i32> zeroinitializer, %6 ; <<4 x i32>>:7 [#uses=1]
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bitcast <4 x i32> %7 to <4 x float> ; <<4 x float>>:8 [#uses=1]
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fmul <4 x float> zeroinitializer, %8 ; <<4 x float>>:9 [#uses=1]
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bitcast <4 x float> %9 to <4 x i32> ; <<4 x i32>>:10 [#uses=1]
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or <4 x i32> %10, zeroinitializer ; <<4 x i32>>:11 [#uses=1]
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bitcast <4 x i32> %11 to <4 x float> ; <<4 x float>>:12 [#uses=1]
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fmul <4 x float> %12, < float 1.000000e+02, float 1.000000e+02, float 1.000000e+02, float 1.000000e+02 > ; <<4 x float>>:13 [#uses=1]
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fsub <4 x float> %13, < float 1.000000e+02, float 1.000000e+02, float 1.000000e+02, float 1.000000e+02 > ; <<4 x float>>:14 [#uses=1]
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extractelement <4 x float> %14, i32 3 ; <float>:15 [#uses=1]
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call float @fmaxf( float 0.000000e+00, float %15 ) ; <float>:16 [#uses=0]
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br label %bb.nph
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._crit_edge: ; preds = %0
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ret void
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}
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declare float @fmaxf(float, float)
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