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[ARM] Add Thumb-2 code size optimization test for ASR (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216746 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -18,3 +18,12 @@ entry:
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%shr = ashr i32 %a, 13
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ret i32 %shr
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}
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define i32 @asr-reg(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: "asr-reg":
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; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
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entry:
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%shr = ashr i32 %a, %b
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ret i32 %shr
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}
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