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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Minor cleanup patch, no functionality changes. Written by Jim Laskey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22727 91177308-0d34-0410-b5e6-96231b3b80d8
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2f46055cc2
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59b21c25d4
@ -635,13 +635,13 @@ static bool isRotateAndMask(unsigned Opcode, unsigned Shift, unsigned Mask,
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return false;
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}
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// isImmediate - This method tests to see if a constant operand.
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isImmediate(SDOperand N, unsigned& Imm) {
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static bool isIntImmediate(SDOperand N, unsigned& Imm) {
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// test for constant
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if (N.getOpcode() == ISD::Constant) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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// retrieve value
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Imm = (unsigned)cast<ConstantSDNode>(N)->getSignExtended();
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Imm = (unsigned)CN->getSignExtended();
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// passes muster
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return true;
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}
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@ -654,14 +654,14 @@ static bool isImmediate(SDOperand N, unsigned& Imm) {
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static bool isOprShiftImm(SDOperand N, unsigned& Opc, unsigned& SH) {
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Opc = N.getOpcode();
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return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
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isImmediate(N.getOperand(1), SH) && SH < 32;
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isIntImmediate(N.getOperand(1), SH) && SH < 32;
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}
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// isOprNot - Returns true if the specified operand is an xor with immediate -1.
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static bool isOprNot(SDOperand N) {
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unsigned Imm;
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return N.getOpcode() == ISD::XOR &&
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isImmediate(N.getOperand(1), Imm) && (signed)Imm == -1;
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isIntImmediate(N.getOperand(1), Imm) && (signed)Imm == -1;
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}
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// Immediate constant composers.
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@ -1079,7 +1079,7 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
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unsigned ISel::FoldIfWideZeroExtend(SDOperand N) {
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unsigned C, MB, ME;
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if (N.getOpcode() == ISD::AND &&
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isImmediate(N.getOperand(1), C) && isRunOfOnes(C, MB, ME) &&
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isIntImmediate(N.getOperand(1), C) && isRunOfOnes(C, MB, ME) &&
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MB <= 26 && ME == 31)
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return SelectExpr(N.getOperand(0));
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else
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@ -1103,7 +1103,7 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
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Idx = getCRIdxForSetCC(SetCC->getCondition(), Inv);
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// Use U to determine whether the SETCC immediate range is signed or not.
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if (isImmediate(SetCC->getOperand(1), Tmp2) &&
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if (isIntImmediate(SetCC->getOperand(1), Tmp2) &&
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((U && isUInt16(Tmp2)) || (!U && isInt16(Tmp2)))) {
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Tmp2 = Lo16(Tmp2);
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// For comparisons against zero, we can implicity set CR0 if a recording
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@ -1192,7 +1192,7 @@ unsigned ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
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unsigned imm = 0, opcode = N.getOpcode();
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if (N.getOpcode() == ISD::ADD) {
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bool isFrame = N.getOperand(0).getOpcode() == ISD::FrameIndex;
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if (isImmediate(N.getOperand(1), imm) && isInt16(imm)) {
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
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offset = Lo16(imm);
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if (isFrame) {
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++FrameOff;
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@ -1636,7 +1636,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isImmediate(N.getOperand(1), Tmp2)) {
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if (isIntImmediate(N.getOperand(1), Tmp2)) {
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Tmp3 = HA16(Tmp2);
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Tmp2 = Lo16(Tmp2);
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if (Tmp2 && Tmp3) {
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@ -1656,7 +1656,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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case ISD::AND:
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if (isImmediate(N.getOperand(1), Tmp2)) {
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if (isIntImmediate(N.getOperand(1), Tmp2)) {
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if (isShiftedMask_32(Tmp2) || isShiftedMask_32(~Tmp2)) {
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unsigned SH, MB, ME;
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Opc = Recording ? PPC::RLWINMo : PPC::RLWINM;
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@ -1707,7 +1707,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isImmediate(N.getOperand(1), Tmp2)) {
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if (isIntImmediate(N.getOperand(1), Tmp2)) {
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Tmp3 = Hi16(Tmp2);
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Tmp2 = Lo16(Tmp2);
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if (Tmp2 && Tmp3) {
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@ -1730,7 +1730,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::XOR: {
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// Check for EQV: xor, (xor a, -1), b
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if (N.getOperand(0).getOpcode() == ISD::XOR &&
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isImmediate(N.getOperand(0).getOperand(1), Tmp2) &&
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isIntImmediate(N.getOperand(0).getOperand(1), Tmp2) &&
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(signed)Tmp2 == -1) {
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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@ -1763,7 +1763,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isImmediate(N.getOperand(1), Tmp2)) {
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if (isIntImmediate(N.getOperand(1), Tmp2)) {
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Tmp3 = Hi16(Tmp2);
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Tmp2 = Lo16(Tmp2);
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if (Tmp2 && Tmp3) {
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@ -1810,11 +1810,11 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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if (isImmediate(N.getOperand(0), Tmp1) && isInt16(Tmp1)) {
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if (isIntImmediate(N.getOperand(0), Tmp1) && isInt16(Tmp1)) {
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
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return Result;
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} else if (isImmediate(N.getOperand(1), Tmp2)) {
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} else if (isIntImmediate(N.getOperand(1), Tmp2)) {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = -Tmp2;
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Tmp3 = HA16(Tmp2);
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@ -1837,7 +1837,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::MUL:
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isImmediate(N.getOperand(1), Tmp2) && isInt16(Tmp2)) {
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if (isIntImmediate(N.getOperand(1), Tmp2) && isInt16(Tmp2)) {
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Tmp2 = Lo16(Tmp2);
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BuildMI(BB, PPC::MULLI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
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} else {
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@ -1861,7 +1861,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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case ISD::SDIV:
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if (isImmediate(N.getOperand(1), Tmp3)) {
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if (isIntImmediate(N.getOperand(1), Tmp3)) {
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if ((signed)Tmp3 > 0 && isPowerOf2_32(Tmp3)) {
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Tmp3 = Log2_32(Tmp3);
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Tmp1 = MakeReg(MVT::i32);
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@ -1884,7 +1884,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::UDIV:
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// If this is a divide by constant, we can emit code using some magic
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// constants to implement it as a multiply instead.
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if (isImmediate(N.getOperand(1), Tmp3)) {
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if (isIntImmediate(N.getOperand(1), Tmp3)) {
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if (opcode == ISD::SDIV) {
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if ((signed)Tmp3 < -1 || (signed)Tmp3 > 1) {
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ExprMap.erase(N);
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