From 59b3300664d062bf04159eacaeb44d6c729e6a8c Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Thu, 18 Jul 2013 11:53:22 +0000 Subject: [PATCH] [ARMv8] Add NEON instructions VCVT{A, N, P, M}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186574 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/IntrinsicsARM.td | 12 ++++++++ lib/Target/ARM/ARMInstrFormats.td | 29 +++++++++++++++++ lib/Target/ARM/ARMInstrNEON.td | 35 +++++++++++++++++++++ test/MC/ARM/neon-v8.s | 36 ++++++++++++++++++++++ test/MC/ARM/thumb-neon-v8.s | 36 ++++++++++++++++++++++ test/MC/Disassembler/ARM/neon-v8.txt | 36 ++++++++++++++++++++++ test/MC/Disassembler/ARM/thumb-neon-v8.txt | 36 ++++++++++++++++++++++ 7 files changed, 220 insertions(+) diff --git a/include/llvm/IR/IntrinsicsARM.td b/include/llvm/IR/IntrinsicsARM.td index 5ffea24c180..7849e940990 100644 --- a/include/llvm/IR/IntrinsicsARM.td +++ b/include/llvm/IR/IntrinsicsARM.td @@ -127,6 +127,8 @@ class Neon_CvtFxToFP_Intrinsic : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; class Neon_CvtFPToFx_Intrinsic : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>; +class Neon_CvtFPtoInt_1Arg_Intrinsic + : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors. // Besides the table, VTBL has one other v8i8 argument and VTBX has two. @@ -319,6 +321,16 @@ def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic; // Vector Reciprocal Square Root Estimate. def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic; +// Vector Conversions Between Floating-point and Integer +def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic; +def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic; +def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic; +def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic; +def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic; +def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic; +def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic; +def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic; + // Vector Conversions Between Floating-point and Fixed-point. def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic; def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic; diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index a835187e382..1349476d7c7 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -1964,6 +1964,35 @@ class N2V op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, let Inst{5} = Vm{4}; } +// Same as N2V but not predicated. +class N2Vnp op17_16, bits<3> op10_8, bit op7, bit op6, + dag oops, dag iops, InstrItinClass itin, string OpcodeStr, + string Dt, ValueType ResTy, ValueType OpTy, list pattern> + : NeonInp { + bits<5> Vd; + bits<5> Vm; + + // Encode instruction operands + let Inst{22} = Vd{4}; + let Inst{15-12} = Vd{3-0}; + let Inst{5} = Vm{4}; + let Inst{3-0} = Vm{3-0}; + + // Encode constant bits + let Inst{27-23} = 0b00111; + let Inst{21-20} = 0b11; + let Inst{19-18} = 0b10; + let Inst{17-16} = op17_16; + let Inst{11} = 0; + let Inst{10-8} = op10_8; + let Inst{7} = op7; + let Inst{6} = op6; + let Inst{4} = 0; + + let DecoderNamespace = "NEON"; +} + // Same as N2V except it doesn't have a datatype suffix. class N2VX op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index f389909b74f..d707e588737 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -2379,6 +2379,21 @@ class N2VQInt op24_23, bits<2> op21_20, bits<2> op19_18, (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>; +// Same as above, but not predicated. +class N2VDIntnp op17_16, bits<3> op10_8, bit op7, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> + : N2Vnp; + +class N2VQIntnp op17_16, bits<3> op10_8, bit op7, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> + : N2Vnp; + // Narrow 2-register operations. class N2VN op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, @@ -5431,6 +5446,26 @@ def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32", def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32", v4f32, v4i32, uint_to_fp>; +// VCVT{A, N, P, M} +multiclass VCVT_FPI op10_8, SDPatternOperator IntS, + SDPatternOperator IntU> { + let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in { + def SD : N2VDIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op), + "s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>; + def SQ : N2VQIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op), + "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>; + def UD : N2VDIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op), + "u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>; + def UQ : N2VQIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op), + "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>; + } +} + +defm VCVTAn : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>; +defm VCVTNn : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>; +defm VCVTPn : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>; +defm VCVTMn : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>; + // VCVT : Vector Convert Between Floating-Point and Fixed-Point. let DecoderMethod = "DecodeVCVTD" in { def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32", diff --git a/test/MC/ARM/neon-v8.s b/test/MC/ARM/neon-v8.s index cc9fb3aebf3..06a22f7c4fd 100644 --- a/test/MC/ARM/neon-v8.s +++ b/test/MC/ARM/neon-v8.s @@ -8,3 +8,39 @@ vminnm.f32 d5, d4, d30 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3] vminnm.f32 q0, q13, q2 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0xd4,0x0f,0x2a,0xf3] + +vcvta.s32.f32 d4, d6 +@ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0x06,0x40,0xbb,0xf3] +vcvta.u32.f32 d12, d10 +@ CHECK: vcvta.u32.f32 d12, d10 @ encoding: [0x8a,0xc0,0xbb,0xf3] +vcvta.s32.f32 q4, q6 +@ CHECK: vcvta.s32.f32 q4, q6 @ encoding: [0x4c,0x80,0xbb,0xf3] +vcvta.u32.f32 q4, q10 +@ CHECK: vcvta.u32.f32 q4, q10 @ encoding: [0xe4,0x80,0xbb,0xf3] + +vcvtm.s32.f32 d1, d30 +@ CHECK: vcvtm.s32.f32 d1, d30 @ encoding: [0x2e,0x13,0xbb,0xf3] +vcvtm.u32.f32 d12, d10 +@ CHECK: vcvtm.u32.f32 d12, d10 @ encoding: [0x8a,0xc3,0xbb,0xf3] +vcvtm.s32.f32 q1, q10 +@ CHECK: vcvtm.s32.f32 q1, q10 @ encoding: [0x64,0x23,0xbb,0xf3] +vcvtm.u32.f32 q13, q1 +@ CHECK: vcvtm.u32.f32 q13, q1 @ encoding: [0xc2,0xa3,0xfb,0xf3] + +vcvtn.s32.f32 d15, d17 +@ CHECK: vcvtn.s32.f32 d15, d17 @ encoding: [0x21,0xf1,0xbb,0xf3] +vcvtn.u32.f32 d5, d3 +@ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0x83,0x51,0xbb,0xf3] +vcvtn.s32.f32 q3, q8 +@ CHECK: vcvtn.s32.f32 q3, q8 @ encoding: [0x60,0x61,0xbb,0xf3] +vcvtn.u32.f32 q5, q3 +@ CHECK: vcvtn.u32.f32 q5, q3 @ encoding: [0xc6,0xa1,0xbb,0xf3] + +vcvtp.s32.f32 d11, d21 +@ CHECK: vcvtp.s32.f32 d11, d21 @ encoding: [0x25,0xb2,0xbb,0xf3] +vcvtp.u32.f32 d14, d23 +@ CHECK: vcvtp.u32.f32 d14, d23 @ encoding: [0xa7,0xe2,0xbb,0xf3] +vcvtp.s32.f32 q4, q15 +@ CHECK: vcvtp.s32.f32 q4, q15 @ encoding: [0x6e,0x82,0xbb,0xf3] +vcvtp.u32.f32 q9, q8 +@ CHECK: vcvtp.u32.f32 q9, q8 @ encoding: [0xe0,0x22,0xfb,0xf3] diff --git a/test/MC/ARM/thumb-neon-v8.s b/test/MC/ARM/thumb-neon-v8.s index eafd271e64b..df40238757c 100644 --- a/test/MC/ARM/thumb-neon-v8.s +++ b/test/MC/ARM/thumb-neon-v8.s @@ -8,3 +8,39 @@ vminnm.f32 d5, d4, d30 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f] vminnm.f32 q0, q13, q2 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0x2a,0xff,0xd4,0x0f] + +vcvta.s32.f32 d4, d6 +@ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0xbb,0xff,0x06,0x40] +vcvta.u32.f32 d12, d10 +@ CHECK: vcvta.u32.f32 d12, d10 @ encoding: [0xbb,0xff,0x8a,0xc0] +vcvta.s32.f32 q4, q6 +@ CHECK: vcvta.s32.f32 q4, q6 @ encoding: [0xbb,0xff,0x4c,0x80] +vcvta.u32.f32 q4, q10 +@ CHECK: vcvta.u32.f32 q4, q10 @ encoding: [0xbb,0xff,0xe4,0x80] + +vcvtm.s32.f32 d1, d30 +@ CHECK: vcvtm.s32.f32 d1, d30 @ encoding: [0xbb,0xff,0x2e,0x13] +vcvtm.u32.f32 d12, d10 +@ CHECK: vcvtm.u32.f32 d12, d10 @ encoding: [0xbb,0xff,0x8a,0xc3] +vcvtm.s32.f32 q1, q10 +@ CHECK: vcvtm.s32.f32 q1, q10 @ encoding: [0xbb,0xff,0x64,0x23] +vcvtm.u32.f32 q13, q1 +@ CHECK: vcvtm.u32.f32 q13, q1 @ encoding: [0xfb,0xff,0xc2,0xa3] + +vcvtn.s32.f32 d15, d17 +@ CHECK: vcvtn.s32.f32 d15, d17 @ encoding: [0xbb,0xff,0x21,0xf1] +vcvtn.u32.f32 d5, d3 +@ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0xbb,0xff,0x83,0x51] +vcvtn.s32.f32 q3, q8 +@ CHECK: vcvtn.s32.f32 q3, q8 @ encoding: [0xbb,0xff,0x60,0x61] +vcvtn.u32.f32 q5, q3 +@ CHECK: vcvtn.u32.f32 q5, q3 @ encoding: [0xbb,0xff,0xc6,0xa1] + +vcvtp.s32.f32 d11, d21 +@ CHECK: vcvtp.s32.f32 d11, d21 @ encoding: [0xbb,0xff,0x25,0xb2] +vcvtp.u32.f32 d14, d23 +@ CHECK: vcvtp.u32.f32 d14, d23 @ encoding: [0xbb,0xff,0xa7,0xe2] +vcvtp.s32.f32 q4, q15 +@ CHECK: vcvtp.s32.f32 q4, q15 @ encoding: [0xbb,0xff,0x6e,0x82] +vcvtp.u32.f32 q9, q8 +@ CHECK: vcvtp.u32.f32 q9, q8 @ encoding: [0xfb,0xff,0xe0,0x22] diff --git a/test/MC/Disassembler/ARM/neon-v8.txt b/test/MC/Disassembler/ARM/neon-v8.txt index 188d475b093..4e9bf3f7def 100644 --- a/test/MC/Disassembler/ARM/neon-v8.txt +++ b/test/MC/Disassembler/ARM/neon-v8.txt @@ -8,3 +8,39 @@ # CHECK: vminnm.f32 d5, d4, d30 0xd4 0x0f 0x2a 0xf3 # CHECK: vminnm.f32 q0, q13, q2 + +0x06 0x40 0xbb 0xf3 +# CHECK: vcvta.s32.f32 d4, d6 +0x8a 0xc0 0xbb 0xf3 +# CHECK: vcvta.u32.f32 d12, d10 +0x4c 0x80 0xbb 0xf3 +# CHECK: vcvta.s32.f32 q4, q6 +0xe4 0x80 0xbb 0xf3 +# CHECK: vcvta.u32.f32 q4, q10 + +0x2e 0x13 0xbb 0xf3 +# CHECK: vcvtm.s32.f32 d1, d30 +0x8a 0xc3 0xbb 0xf3 +# CHECK: vcvtm.u32.f32 d12, d10 +0x64 0x23 0xbb 0xf3 +# CHECK: vcvtm.s32.f32 q1, q10 +0xc2 0xa3 0xfb 0xf3 +# CHECK: vcvtm.u32.f32 q13, q1 + +0x21 0xf1 0xbb 0xf3 +# CHECK: vcvtn.s32.f32 d15, d17 +0x83 0x51 0xbb 0xf3 +# CHECK: vcvtn.u32.f32 d5, d3 +0x60 0x61 0xbb 0xf3 +# CHECK: vcvtn.s32.f32 q3, q8 +0xc6 0xa1 0xbb 0xf3 +# CHECK: vcvtn.u32.f32 q5, q3 + +0x25 0xb2 0xbb 0xf3 +# CHECK: vcvtp.s32.f32 d11, d21 +0xa7 0xe2 0xbb 0xf3 +# CHECK: vcvtp.u32.f32 d14, d23 +0x6e 0x82 0xbb 0xf3 +# CHECK: vcvtp.s32.f32 q4, q15 +0xe0 0x22 0xfb 0xf3 +# CHECK: vcvtp.u32.f32 q9, q8 diff --git a/test/MC/Disassembler/ARM/thumb-neon-v8.txt b/test/MC/Disassembler/ARM/thumb-neon-v8.txt index c777dc6912a..f025b8b2ab8 100644 --- a/test/MC/Disassembler/ARM/thumb-neon-v8.txt +++ b/test/MC/Disassembler/ARM/thumb-neon-v8.txt @@ -8,3 +8,39 @@ # CHECK: vminnm.f32 d5, d4, d30 0x2a 0xff 0xd4 0x0f # CHECK: vminnm.f32 q0, q13, q2 + +0xbb 0xff 0x06 0x40 +# CHECK: vcvta.s32.f32 d4, d6 +0xbb 0xff 0x8a 0xc0 +# CHECK: vcvta.u32.f32 d12, d10 +0xbb 0xff 0x4c 0x80 +# CHECK: vcvta.s32.f32 q4, q6 +0xbb 0xff 0xe4 0x80 +# CHECK: vcvta.u32.f32 q4, q10 + +0xbb 0xff 0x2e 0x13 +# CHECK: vcvtm.s32.f32 d1, d30 +0xbb 0xff 0x8a 0xc3 +# CHECK: vcvtm.u32.f32 d12, d10 +0xbb 0xff 0x64 0x23 +# CHECK: vcvtm.s32.f32 q1, q10 +0xfb 0xff 0xc2 0xa3 +# CHECK: vcvtm.u32.f32 q13, q1 + +0xbb 0xff 0x21 0xf1 +# CHECK: vcvtn.s32.f32 d15, d17 +0xbb 0xff 0x83 0x51 +# CHECK: vcvtn.u32.f32 d5, d3 +0xbb 0xff 0x60 0x61 +# CHECK: vcvtn.s32.f32 q3, q8 +0xbb 0xff 0xc6 0xa1 +# CHECK: vcvtn.u32.f32 q5, q3 + +0xbb 0xff 0x25 0xb2 +# CHECK: vcvtp.s32.f32 d11, d21 +0xbb 0xff 0xa7 0xe2 +# CHECK: vcvtp.u32.f32 d14, d23 +0xbb 0xff 0x6e 0x82 +# CHECK: vcvtp.s32.f32 q4, q15 +0xfb 0xff 0xe0 0x22 +# CHECK: vcvtp.u32.f32 q9, q8