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MachineInstr: Use range-based for loops. NFC.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230142 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
2015-02-21 17:08:08 +00:00
parent 7efcb3338c
commit 59d81dbafb
1 changed files with 20 additions and 34 deletions
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54
lib/CodeGen/MachineInstr.cpp
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@ -625,8 +625,8 @@ MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
Operands = MF.allocateOperandArray(CapOperands); Operands = MF.allocateOperandArray(CapOperands);
// Copy operands. // Copy operands.
for (unsigned i = 0; i != MI.getNumOperands(); ++i) for (const MachineOperand &MO : MI.operands())
addOperand(MF, MI.getOperand(i)); addOperand(MF, MO);
// Copy all the sensible flags. // Copy all the sensible flags.
setFlags(MI.Flags); setFlags(MI.Flags);
@ -645,18 +645,18 @@ MachineRegisterInfo *MachineInstr::getRegInfo() {
/// this instruction from their respective use lists. This requires that the /// this instruction from their respective use lists. This requires that the
/// operands already be on their use lists. /// operands already be on their use lists.
void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) for (MachineOperand &MO : operands())
if (Operands[i].isReg()) if (MO.isReg())
MRI.removeRegOperandFromUseList(&Operands[i]); MRI.removeRegOperandFromUseList(&MO);
} }
/// AddRegOperandsToUseLists - Add all of the register operands in /// AddRegOperandsToUseLists - Add all of the register operands in
/// this instruction from their respective use lists. This requires that the /// this instruction from their respective use lists. This requires that the
/// operands not be on their use lists yet. /// operands not be on their use lists yet.
void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) for (MachineOperand &MO : operands())
if (Operands[i].isReg()) if (MO.isReg())
MRI.addRegOperandToUseList(&Operands[i]); MRI.addRegOperandToUseList(&MO);
} }
void MachineInstr::addOperand(const MachineOperand &Op) { void MachineInstr::addOperand(const MachineOperand &Op) {
@ -920,8 +920,7 @@ void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
MachineInstr *MI = (MachineInstr *)this; MachineInstr *MI = (MachineInstr *)this;
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (const MachineOperand &MO : MI->operands()) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isDef()) if (!MO.isReg() || !MO.isDef())
continue; continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
@ -1324,8 +1323,7 @@ unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
/// clearKillInfo - Clears kill flags on all operands. /// clearKillInfo - Clears kill flags on all operands.
/// ///
void MachineInstr::clearKillInfo() { void MachineInstr::clearKillInfo() {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (MachineOperand &MO : operands()) {
MachineOperand &MO = getOperand(i);
if (MO.isReg() && MO.isUse()) if (MO.isReg() && MO.isUse())
MO.setIsKill(false); MO.setIsKill(false);
} }
@ -1338,15 +1336,13 @@ void MachineInstr::substituteRegister(unsigned FromReg,
if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
if (SubIdx) if (SubIdx)
ToReg = RegInfo.getSubReg(ToReg, SubIdx); ToReg = RegInfo.getSubReg(ToReg, SubIdx);
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (MachineOperand &MO : operands()) {
MachineOperand &MO = getOperand(i);
if (!MO.isReg() || MO.getReg() != FromReg) if (!MO.isReg() || MO.getReg() != FromReg)
continue; continue;
MO.substPhysReg(ToReg, RegInfo); MO.substPhysReg(ToReg, RegInfo);
} }
} else { } else {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (MachineOperand &MO : operands()) {
MachineOperand &MO = getOperand(i);
if (!MO.isReg() || MO.getReg() != FromReg) if (!MO.isReg() || MO.getReg() != FromReg)
continue; continue;
MO.substVirtReg(ToReg, SubIdx, RegInfo); MO.substVirtReg(ToReg, SubIdx, RegInfo);
@ -1489,8 +1485,7 @@ bool MachineInstr::hasUnmodeledSideEffects() const {
/// allDefsAreDead - Return true if all the defs of this instruction are dead. /// allDefsAreDead - Return true if all the defs of this instruction are dead.
/// ///
bool MachineInstr::allDefsAreDead() const { bool MachineInstr::allDefsAreDead() const {
for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { for (const MachineOperand &MO : operands()) {
const MachineOperand &MO = getOperand(i);
if (!MO.isReg() || MO.isUse()) if (!MO.isReg() || MO.isUse())
continue; continue;
if (!MO.isDead()) if (!MO.isDead())
@ -1821,8 +1816,7 @@ void MachineInstr::clearRegisterKills(unsigned Reg,
const TargetRegisterInfo *RegInfo) { const TargetRegisterInfo *RegInfo) {
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) if (!TargetRegisterInfo::isPhysicalRegister(Reg))
RegInfo = nullptr; RegInfo = nullptr;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (MachineOperand &MO : operands()) {
MachineOperand &MO = getOperand(i);
if (!MO.isReg() || !MO.isUse() || !MO.isKill()) if (!MO.isReg() || !MO.isUse() || !MO.isKill())
continue; continue;
unsigned OpReg = MO.getReg(); unsigned OpReg = MO.getReg();
@ -1906,8 +1900,7 @@ void MachineInstr::addRegisterDefined(unsigned Reg,
if (MO) if (MO)
return; return;
} else { } else {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (const MachineOperand &MO : operands()) {
const MachineOperand &MO = getOperand(i);
if (MO.isReg() && MO.getReg() == Reg && MO.isDef() && if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
MO.getSubReg() == 0) MO.getSubReg() == 0)
return; return;
@ -1921,8 +1914,7 @@ void MachineInstr::addRegisterDefined(unsigned Reg,
void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
const TargetRegisterInfo &TRI) { const TargetRegisterInfo &TRI) {
bool HasRegMask = false; bool HasRegMask = false;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (MachineOperand &MO : operands()) {
MachineOperand &MO = getOperand(i);
if (MO.isRegMask()) { if (MO.isRegMask()) {
HasRegMask = true; HasRegMask = true;
continue; continue;
@ -1930,15 +1922,10 @@ void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
if (!MO.isReg() || !MO.isDef()) continue; if (!MO.isReg() || !MO.isDef()) continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue; if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
bool Dead = true;
for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
I != E; ++I)
if (TRI.regsOverlap(*I, Reg)) {
Dead = false;
break;
}
// If there are no uses, including partial uses, the def is dead. // If there are no uses, including partial uses, the def is dead.
if (Dead) MO.setIsDead(); if (std::none_of(UsedRegs.begin(), UsedRegs.end(),
[&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
MO.setIsDead();
} }
// This is a call with a register mask operand. // This is a call with a register mask operand.
@ -1955,8 +1942,7 @@ MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
SmallVector<size_t, 8> HashComponents; SmallVector<size_t, 8> HashComponents;
HashComponents.reserve(MI->getNumOperands() + 1); HashComponents.reserve(MI->getNumOperands() + 1);
HashComponents.push_back(MI->getOpcode()); HashComponents.push_back(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (const MachineOperand &MO : MI->operands()) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isDef() && if (MO.isReg() && MO.isDef() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) TargetRegisterInfo::isVirtualRegister(MO.getReg()))
continue; // Skip virtual register defs. continue; // Skip virtual register defs.