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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Add assembler support for all CI and VI VOP1 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235629 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
f0924551e6
commit
59edae9b85
@ -147,6 +147,18 @@ def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
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"GCN3Encoding",
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"true",
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"Encoding format for VI">;
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def FeatureCIInsts : SubtargetFeature<"ci-insts",
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"CIInsts",
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"true",
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"Additional intstructions for CI+">;
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// Dummy feature used to disable assembler instructions.
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def FeatureDisable : SubtargetFeature<"",
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"FeatureDisable","true",
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"Dummy feature to disable assembler"
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" instructions">;
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class SubtargetFeatureGeneration <string Value,
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list<SubtargetFeature> Implies> :
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SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
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@ -177,12 +189,12 @@ def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
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FeatureGCN1Encoding]>;
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FeatureGCN1Encoding, FeatureCIInsts]>;
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def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
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FeatureGCN3Encoding]>;
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FeatureGCN3Encoding, FeatureCIInsts]>;
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//===----------------------------------------------------------------------===//
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@ -211,11 +223,19 @@ def NullALU : InstrItinClass;
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// Predicate helper class
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//===----------------------------------------------------------------------===//
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def TruePredicate : Predicate<"true">;
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def isSICI : Predicate<
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"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
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"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
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>, AssemblerPredicate<"FeatureGCN1Encoding">;
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class PredicateControl {
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Predicate SubtargetPredicate;
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Predicate SIAssemblerPredicate = isSICI;
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list<Predicate> AssemblerPredicates = [];
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Predicate AssemblerPredicate = TruePredicate;
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list<Predicate> OtherPredicates = [];
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list<Predicate> Predicates = !listconcat([SubtargetPredicate],
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list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
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AssemblerPredicates,
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OtherPredicates);
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}
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@ -71,7 +71,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
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EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
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WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
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EnableVGPRSpilling(false), SGPRInitBug(false),
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IsGCN(false), GCN1Encoding(false), GCN3Encoding(false),
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IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false),
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FrameLowering(TargetFrameLowering::StackGrowsUp,
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64 * 16, // Maximum stack alignment (long16)
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0),
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@ -74,6 +74,8 @@ private:
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bool IsGCN;
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bool GCN1Encoding;
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bool GCN3Encoding;
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bool CIInsts;
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bool FeatureDisable;
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AMDGPUFrameLowering FrameLowering;
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std::unique_ptr<AMDGPUTargetLowering> TLInfo;
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@ -13,7 +13,7 @@
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def isCIVI : Predicate <
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"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || "
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"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS"
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>;
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>, AssemblerPredicate<"FeatureCIInsts">;
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//===----------------------------------------------------------------------===//
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// VOP1 Instructions
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@ -6,16 +6,14 @@
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def isSICI : Predicate<
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"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
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"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
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>, AssemblerPredicate<"FeatureGCN1Encoding">;
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def isCI : Predicate<"Subtarget->getGeneration() "
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">= AMDGPUSubtarget::SEA_ISLANDS">;
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def isVI : Predicate <
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"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
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AssemblerPredicate<"FeatureGCN3Encoding">;
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def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
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class vop {
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field bits<9> SI3;
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field bits<10> VI3;
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@ -933,6 +931,12 @@ class VOPProfile <list<ValueType> _ArgVT> {
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field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
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}
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// FIXME: I think these F16 profiles will need to use f16 types in order
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// for the instruction patterns to work.
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def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>;
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def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>;
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def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>;
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def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
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def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
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def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
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@ -1011,11 +1015,15 @@ class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
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class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
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VOP1<op.SI, outs, ins, asm, []>,
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SIMCInstr <opName#"_e32", SISubtarget.SI>;
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SIMCInstr <opName#"_e32", SISubtarget.SI> {
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let AssemblerPredicate = SIAssemblerPredicate;
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}
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class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
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VOP1<op.VI, outs, ins, asm, []>,
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SIMCInstr <opName#"_e32", SISubtarget.VI>;
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SIMCInstr <opName#"_e32", SISubtarget.VI> {
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let AssemblerPredicates = [isVI];
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}
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multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
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string opName> {
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@ -9,6 +9,36 @@
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// Instruction definitions for VI and newer.
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//===----------------------------------------------------------------------===//
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let SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI in {
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//===----------------------------------------------------------------------===//
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// VOP1 Instructions
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//===----------------------------------------------------------------------===//
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defm V_CVT_F16_U16 : VOP1Inst <vop1<0, 0x39>, "v_cvt_f16_u16", VOP_F16_I16>;
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defm V_CVT_F16_I16 : VOP1Inst <vop1<0, 0x3a>, "v_cvt_f16_i16", VOP_F16_I16>;
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defm V_CVT_U16_F16 : VOP1Inst <vop1<0, 0x3b>, "v_cvt_u16_f16", VOP_I16_F16>;
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defm V_CVT_I16_F16 : VOP1Inst <vop1<0, 0x3c>, "v_cvt_i16_f16", VOP_I16_F16>;
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defm V_RCP_F16 : VOP1Inst <vop1<0, 0x3d>, "v_rcp_f16", VOP_F16_F16>;
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defm V_SQRT_F16 : VOP1Inst <vop1<0, 0x3e>, "v_sqrt_f16", VOP_F16_F16>;
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defm V_RSQ_F16 : VOP1Inst <vop1<0, 0x3f>, "v_rsq_f16", VOP_F16_F16>;
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defm V_LOG_F16 : VOP1Inst <vop1<0, 0x40>, "v_log_f16", VOP_F16_F16>;
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defm V_EXP_F16 : VOP1Inst <vop1<0, 0x41>, "v_exp_f16", VOP_F16_F16>;
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defm V_FREXP_MANT_F16 : VOP1Inst <vop1<0, 0x42>, "v_frexp_mant_f16",
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VOP_F16_F16
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>;
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defm V_FREXP_EXP_I16_F16 : VOP1Inst <vop1<0, 0x43>, "v_frexp_exp_i16_f16",
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VOP_I16_F16
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>;
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defm V_FLOOR_F16 : VOP1Inst <vop1<0, 0x44>, "v_floor_f16", VOP_F16_F16>;
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defm V_CEIL_F16 : VOP1Inst <vop1<0, 0x45>, "v_ceil_f16", VOP_F16_F16>;
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defm V_TRUNC_F16 : VOP1Inst <vop1<0, 0x46>, "v_trunc_f16", VOP_F16_F16>;
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defm V_RNDNE_F16 : VOP1Inst <vop1<0, 0x47>, "v_rndne_f16", VOP_F16_F16>;
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defm V_FRACT_F16 : VOP1Inst <vop1<0, 0x48>, "v_fract_f16", VOP_F16_F16>;
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defm V_SIN_F16 : VOP1Inst <vop1<0, 0x49>, "v_sin_f16", VOP_F16_F16>;
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defm V_COS_F16 : VOP1Inst <vop1<0, 0x4a>, "v_cos_f16", VOP_F16_F16>;
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} // End SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI
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//===----------------------------------------------------------------------===//
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// SMEM Patterns
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@ -1,182 +1,357 @@
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// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
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// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
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// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
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// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
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// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
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// CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
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// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
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// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
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// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
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// GCN: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
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v_nop
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// CHECK: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
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// GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
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v_mov_b32 v1, v2
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// CHECK: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
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// GCN: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
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v_readfirstlane_b32 s1, v2
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// CHECK: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e]
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// GCN: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e]
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v_cvt_i32_f64 v1, v[2:3]
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// CHECK: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
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// GCN: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
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v_cvt_f64_i32 v[1:2], v2
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// CHECK: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e]
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// GCN: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e]
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v_cvt_f32_i32 v1, v2
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// CHECK: v_cvt_f32_u32_e32 v1, v2 ; encoding: [0x02,0x0d,0x02,0x7e]
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// GCN: v_cvt_f32_u32_e32 v1, v2 ; encoding: [0x02,0x0d,0x02,0x7e]
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v_cvt_f32_u32 v1, v2
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// CHECK: v_cvt_u32_f32_e32 v1, v2 ; encoding: [0x02,0x0f,0x02,0x7e
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// GCN: v_cvt_u32_f32_e32 v1, v2 ; encoding: [0x02,0x0f,0x02,0x7e
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v_cvt_u32_f32 v1, v2
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// CHECK: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e]
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// GCN: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e]
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v_cvt_i32_f32 v1, v2
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// CHECK: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e]
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// SICI: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e]
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// NOVI: error: instruction not supported on this GPU
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v_mov_fed_b32 v1, v2
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// CHECK: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e]
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// GCN: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e]
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v_cvt_f16_f32 v1, v2
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// CHECK: v_cvt_f32_f16_e32 v1, v2 ; encoding: [0x02,0x17,0x02,0x7e]
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// GCN: v_cvt_f32_f16_e32 v1, v2 ; encoding: [0x02,0x17,0x02,0x7e]
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v_cvt_f32_f16 v1, v2
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// CHECK: v_cvt_rpi_i32_f32_e32 v1, v2 ; encoding: [0x02,0x19,0x02,0x7e]
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// GCN: v_cvt_rpi_i32_f32_e32 v1, v2 ; encoding: [0x02,0x19,0x02,0x7e]
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v_cvt_rpi_i32_f32 v1, v2
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// CHECK: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e]
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// GCN: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e]
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v_cvt_flr_i32_f32 v1, v2
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// CHECK: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e]
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// GCN: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e]
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v_cvt_off_f32_i4_e32 v1, v2
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// CHECK: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e]
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// GCN: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e]
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v_cvt_f32_f64 v1, v[2:3]
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// CHECK: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e]
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// GCN: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e]
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v_cvt_f64_f32 v[1:2], v2
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// CHECK: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e]
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// GCN: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e]
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v_cvt_f32_ubyte0 v1, v2
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// CHECK: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e]
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// GCN: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e]
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v_cvt_f32_ubyte1_e32 v1, v2
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// CHECK: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e]
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// GCN: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e]
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v_cvt_f32_ubyte2 v1, v2
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// CHECK: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e]
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// GCN: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e]
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v_cvt_f32_ubyte3 v1, v2
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// CHECK: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e]
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// GCN: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e]
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v_cvt_u32_f64 v1, v[2:3]
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// CHECK: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e]
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// GCN: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e]
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v_cvt_f64_u32 v[1:2], v2
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// CHECK: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e]
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// NOSI: error: instruction not supported on this GPU
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// NOSI: v_trunc_f64_e32 v[1:2], v[2:3]
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// CIVI: v_trunc_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x2f,0x02,0x7e]
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v_trunc_f64_e32 v[1:2], v[2:3]
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// NOSI: error: instruction not supported on this GPU
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// NOSI: v_ceil_f64_e32 v[1:2], v[2:3]
|
||||
// CIVI: v_ceil_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x31,0x02,0x7e]
|
||||
v_ceil_f64_e32 v[1:2], v[2:3]
|
||||
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: v_rndne_f64_e32 v[1:2], v[2:3]
|
||||
// CIVI: v_rndne_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x33,0x02,0x7e]
|
||||
v_rndne_f64_e32 v[1:2], v[2:3]
|
||||
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: v_floor_f64_e32 v[1:2], v[2:3]
|
||||
// CIVI: v_floor_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x35,0x02,0x7e]
|
||||
v_floor_f64_e32 v[1:2], v[2:3]
|
||||
|
||||
// SICI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e]
|
||||
// VI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x37,0x02,0x7e]
|
||||
v_fract_f32 v1, v2
|
||||
|
||||
// CHECK: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e]
|
||||
// SICI: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e]
|
||||
// VI: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x39,0x02,0x7e]
|
||||
v_trunc_f32 v1, v2
|
||||
|
||||
// CHECK: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e]
|
||||
// SICI: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e]
|
||||
// VI: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x3b,0x02,0x7e]
|
||||
v_ceil_f32 v1, v2
|
||||
|
||||
// CHECK: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e]
|
||||
// SICI: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e]
|
||||
// VI: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x3d,0x02,0x7e]
|
||||
v_rndne_f32 v1, v2
|
||||
|
||||
// CHECK: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e]
|
||||
// SICI: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e]
|
||||
// VI: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x3f,0x02,0x7e]
|
||||
v_floor_f32_e32 v1, v2
|
||||
|
||||
// CHECK: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x4b,0x02,0x7e]
|
||||
// SICI: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x4b,0x02,0x7e]
|
||||
// VI: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e]
|
||||
v_exp_f32 v1, v2
|
||||
|
||||
// CHECK: v_log_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x4d,0x02,0x7e]
|
||||
// SICI: v_log_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x4d,0x02,0x7e]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: v_log_clamp_f32 v1, v2
|
||||
v_log_clamp_f32 v1, v2
|
||||
|
||||
// CHECK: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e]
|
||||
// SICI: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e]
|
||||
// VI: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e]
|
||||
v_log_f32 v1, v2
|
||||
|
||||
// CHECK: v_rcp_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x51,0x02,0x7e]
|
||||
// SICI: v_rcp_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x51,0x02,0x7e]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: v_rcp_clamp_f32 v1, v2
|
||||
v_rcp_clamp_f32 v1, v2
|
||||
|
||||
// CHECK: v_rcp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e]
|
||||
// SICI: v_rcp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: v_rcp_legacy_f32 v1, v2
|
||||
v_rcp_legacy_f32 v1, v2
|
||||
|
||||
// CHECK: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e]
|
||||
// SICI: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e]
|
||||
// VI: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e]
|
||||
v_rcp_f32 v1, v2
|
||||
|
||||
// CHECK: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e]
|
||||
// SICI: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e]
|
||||
// VI: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e]
|
||||
v_rcp_iflag_f32 v1, v2
|
||||
|
||||
// CHECK: v_rsq_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e]
|
||||
// SICI: v_rsq_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: v_rsq_clamp_f32 v1, v2
|
||||
v_rsq_clamp_f32 v1, v2
|
||||
|
||||
// CHECK: v_rsq_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e]
|
||||
// SICI: v_rsq_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: v_rsq_legacy_f32 v1, v2
|
||||
v_rsq_legacy_f32 v1, v2
|
||||
|
||||
// CHECK: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e]
|
||||
// SICI: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e]
|
||||
// VI: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e]
|
||||
v_rsq_f32_e32 v1, v2
|
||||
|
||||
// CHECK: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x5f,0x02,0x7e]
|
||||
// SICI: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x5f,0x02,0x7e]
|
||||
// VI: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4b,0x02,0x7e]
|
||||
v_rcp_f64 v[1:2], v[2:3]
|
||||
|
||||
// CHECK: v_rcp_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x61,0x02,0x7e]
|
||||
// SICI: v_rcp_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x61,0x02,0x7e]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: v_rcp_clamp_f64 v[1:2], v[2:3]
|
||||
v_rcp_clamp_f64 v[1:2], v[2:3]
|
||||
|
||||
// CHECK: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
|
||||
// SICI: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
|
||||
// VI: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4d,0x02,0x7e]
|
||||
v_rsq_f64 v[1:2], v[2:3]
|
||||
|
||||
// CHECK: v_rsq_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e]
|
||||
// SICI: v_rsq_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: v_rsq_clamp_f64 v[1:2], v[2:3]
|
||||
v_rsq_clamp_f64 v[1:2], v[2:3]
|
||||
|
||||
// CHECK: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e]
|
||||
// SICI: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e]
|
||||
// VI: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e]
|
||||
v_sqrt_f32 v1, v2
|
||||
|
||||
// CHECK: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x69,0x02,0x7e]
|
||||
// SICI: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x69,0x02,0x7e]
|
||||
// VI: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x51,0x02,0x7e]
|
||||
v_sqrt_f64 v[1:2], v[2:3]
|
||||
|
||||
// CHECK: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x6b,0x02,0x7e]
|
||||
// SICI: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x6b,0x02,0x7e]
|
||||
// VI: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e]
|
||||
v_sin_f32 v1, v2
|
||||
|
||||
// CHECK: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
|
||||
// SICI: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
|
||||
// VI: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e]
|
||||
v_cos_f32 v1, v2
|
||||
|
||||
// CHECK: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
|
||||
// SICI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
|
||||
// VI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e]
|
||||
v_not_b32 v1, v2
|
||||
|
||||
// CHECK: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
|
||||
// SICI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
|
||||
// VI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e]
|
||||
v_bfrev_b32 v1, v2
|
||||
|
||||
// CHECK: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
|
||||
// SICI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
|
||||
// VI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e]
|
||||
v_ffbh_u32 v1, v2
|
||||
|
||||
// CHECK: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
|
||||
// SICI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
|
||||
// VI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e]
|
||||
v_ffbl_b32 v1, v2
|
||||
|
||||
// CHECK: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
|
||||
// SICI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
|
||||
// VI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x5f,0x02,0x7e]
|
||||
v_ffbh_i32_e32 v1, v2
|
||||
|
||||
// CHECK: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e]
|
||||
// SICI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e]
|
||||
// VI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x61,0x02,0x7e]
|
||||
v_frexp_exp_i32_f64 v1, v[2:3]
|
||||
|
||||
// CHECK: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e]
|
||||
// SICI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e]
|
||||
// VI; v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
|
||||
v_frexp_mant_f64 v[1:2], v[2:3]
|
||||
|
||||
// CHECK: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e]
|
||||
// SICI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e]
|
||||
// VI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e]
|
||||
v_fract_f64 v[1:2], v[2:3]
|
||||
|
||||
// CHECK: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
|
||||
// SICI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
|
||||
// VI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e]
|
||||
v_frexp_exp_i32_f32 v1, v2
|
||||
|
||||
// CHECK: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
|
||||
// SICI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
|
||||
// VI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x69,0x02,0x7e]
|
||||
v_frexp_mant_f32 v1, v2
|
||||
|
||||
// CHECK: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e]
|
||||
// SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e]
|
||||
// VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
|
||||
v_clrexcp
|
||||
|
||||
// CHECK: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
|
||||
// SICI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
|
||||
// VI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
|
||||
v_movreld_b32 v1, v2
|
||||
|
||||
// CHECK: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
|
||||
// SICI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
|
||||
// VI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
|
||||
v_movrels_b32 v1, v2
|
||||
|
||||
// CHECK: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
|
||||
// SICI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
|
||||
// VI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
|
||||
v_movrelsd_b32 v1, v2
|
||||
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: v_log_legacy_f32 v1, v2
|
||||
// CI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]
|
||||
// VI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x99,0x02,0x7e]
|
||||
v_log_legacy_f32 v1, v2
|
||||
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: v_exp_legacy_f32 v1, v2
|
||||
// CI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e]
|
||||
// VI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x97,0x02,0x7e]
|
||||
v_exp_legacy_f32 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_cvt_f16_u16 v1, v2
|
||||
// VI: v_cvt_f16_u16_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
|
||||
v_cvt_f16_u16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_cvt_f16_i16 v1, v2
|
||||
// VI: v_cvt_f16_i16_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
|
||||
v_cvt_f16_i16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_cvt_u16_f16 v1, v2
|
||||
// VI: v_cvt_u16_f16_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
|
||||
v_cvt_u16_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_cvt_i16_f16 v1, v2
|
||||
// VI: v_cvt_i16_f16_e32 v1, v2 ; encoding: [0x02,0x79,0x02,0x7e]
|
||||
v_cvt_i16_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_rcp_f16 v1, v2
|
||||
// VI: v_rcp_f16_e32 v1, v2 ; encoding: [0x02,0x7b,0x02,0x7e]
|
||||
v_rcp_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_sqrt_f16 v1, v2
|
||||
// VI: v_sqrt_f16_e32 v1, v2 ; encoding: [0x02,0x7d,0x02,0x7e]
|
||||
v_sqrt_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_rsq_f16 v1, v2
|
||||
// VI: v_rsq_f16_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
|
||||
v_rsq_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_log_f16 v1, v2
|
||||
// VI: v_log_f16_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
|
||||
v_log_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_exp_f16 v1, v2
|
||||
// VI: v_exp_f16_e32 v1, v2 ; encoding: [0x02,0x83,0x02,0x7e]
|
||||
v_exp_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_frexp_mant_f16 v1, v2
|
||||
// VI: v_frexp_mant_f16_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
|
||||
v_frexp_mant_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_frexp_exp_i16_f16 v1, v2
|
||||
// VI: v_frexp_exp_i16_f16_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
|
||||
v_frexp_exp_i16_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_floor_f16 v1, v2
|
||||
// VI: v_floor_f16_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
|
||||
v_floor_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_ceil_f16 v1, v2
|
||||
// VI: v_ceil_f16_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]
|
||||
v_ceil_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_trunc_f16 v1, v2
|
||||
// VI: v_trunc_f16_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e]
|
||||
v_trunc_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_rndne_f16 v1, v2
|
||||
// VI: v_rndne_f16_e32 v1, v2 ; encoding: [0x02,0x8f,0x02,0x7e]
|
||||
v_rndne_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_fract_f16 v1, v2
|
||||
// VI: v_fract_f16_e32 v1, v2 ; encoding: [0x02,0x91,0x02,0x7e]
|
||||
v_fract_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_sin_f16 v1, v2
|
||||
// VI: v_sin_f16_e32 v1, v2 ; encoding: [0x02,0x93,0x02,0x7e]
|
||||
v_sin_f16 v1, v2
|
||||
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// NOSICI: v_cos_f16 v1, v2
|
||||
// VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e]
|
||||
v_cos_f16 v1, v2
|
||||
|
||||
Loading…
Reference in New Issue
Block a user