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Don't indent cases in a switch, no functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127681 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2011-03-15 15:55:30 +00:00
parent 8ae8cf4559
commit 59f727e57e
1 changed files with 50 additions and 50 deletions
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100
lib/Target/XCore/XCoreISelDAGToDAG.cpp
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@ -157,58 +157,58 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
EVT NVT = N->getValueType(0); EVT NVT = N->getValueType(0);
if (NVT == MVT::i32) { if (NVT == MVT::i32) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: break; default: break;
case ISD::Constant: { case ISD::Constant: {
uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue(); uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
if (immMskBitp(N)) { if (immMskBitp(N)) {
// Transformation function: get the size of a mask // Transformation function: get the size of a mask
// Look for the first non-zero bit // Look for the first non-zero bit
SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val)); SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val));
return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
MVT::i32, MskSize); MVT::i32, MskSize);
}
else if (!isUInt<16>(Val)) {
SDValue CPIdx =
CurDAG->getTargetConstantPool(ConstantInt::get(
Type::getInt32Ty(*CurDAG->getContext()), Val),
TLI.getPointerTy());
return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
MVT::Other, CPIdx,
CurDAG->getEntryNode());
}
break;
} }
case XCoreISD::LADD: { else if (!isUInt<16>(Val)) {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), SDValue CPIdx =
N->getOperand(2) }; CurDAG->getTargetConstantPool(ConstantInt::get(
return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, Type::getInt32Ty(*CurDAG->getContext()), Val),
Ops, 3); TLI.getPointerTy());
return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
MVT::Other, CPIdx,
CurDAG->getEntryNode());
} }
case XCoreISD::LSUB: { break;
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), }
N->getOperand(2) }; case XCoreISD::LADD: {
return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
Ops, 3); N->getOperand(2) };
} return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
case XCoreISD::MACCU: { Ops, 3);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), }
N->getOperand(2), N->getOperand(3) }; case XCoreISD::LSUB: {
return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32, SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
Ops, 4); N->getOperand(2) };
} return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
case XCoreISD::MACCS: { Ops, 3);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), }
N->getOperand(2), N->getOperand(3) }; case XCoreISD::MACCU: {
return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32, SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
Ops, 4); N->getOperand(2), N->getOperand(3) };
} return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
case XCoreISD::LMUL: { Ops, 4);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), }
N->getOperand(2), N->getOperand(3) }; case XCoreISD::MACCS: {
return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
Ops, 4); N->getOperand(2), N->getOperand(3) };
} return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
// Other cases are autogenerated. Ops, 4);
}
case XCoreISD::LMUL: {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
N->getOperand(2), N->getOperand(3) };
return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
Ops, 4);
}
// Other cases are autogenerated.
} }
} }
return SelectCode(N); return SelectCode(N);