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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55975 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -80,6 +80,11 @@ public:
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/// be assigned the value for the given LLVM value.
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unsigned getRegForValue(Value *V);
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/// lookUpRegForValue - Look up the value to see if its value is already
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/// cached in a register. It may be defined by instructions across blocks or
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/// defined locally.
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unsigned lookUpRegForValue(Value *V);
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virtual ~FastISel();
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protected:
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@ -40,6 +40,9 @@ unsigned FastISel::getRegForValue(Value *V) {
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// Don't cache constant materializations. To do so would require
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// tracking what uses they dominate.
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Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
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} else if (isa<GlobalValue>(V)) {
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return TargetMaterializeConstant(dyn_cast<Constant>(V),
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MBB->getParent()->getConstantPool());
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} else if (isa<ConstantPointerNull>(V)) {
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Reg = FastEmit_i(VT, VT, ISD::Constant, 0);
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} else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
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@ -85,6 +88,16 @@ unsigned FastISel::getRegForValue(Value *V) {
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return Reg;
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}
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unsigned FastISel::lookUpRegForValue(Value *V) {
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// Look up the value to see if we already have a register for it. We
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// cache values defined by Instructions across blocks, and other values
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// only locally. This is because Instructions already have the SSA
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// def-dominatess-use requirement enforced.
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if (ValueMap.count(V))
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return ValueMap[V];
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return LocalValueMap[V];
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}
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/// UpdateValueMap - Update the value map to include the new mapping for this
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/// instruction, or insert an extra copy to get the result in a previous
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/// determined register.
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@ -74,7 +74,8 @@ private:
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bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
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unsigned &ResultReg);
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bool X86SelectConstAddr(Value *V, unsigned &Op0, bool isCall = false);
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bool X86SelectConstAddr(Value *V, unsigned &Op0,
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bool isCall = false, bool inReg = false);
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bool X86SelectLoad(Instruction *I);
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@ -285,7 +286,8 @@ bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
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/// X86SelectConstAddr - Select and emit code to materialize constant address.
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///
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bool X86FastISel::X86SelectConstAddr(Value *V, unsigned &Op0, bool isCall) {
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bool X86FastISel::X86SelectConstAddr(Value *V, unsigned &Op0,
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bool isCall, bool inReg) {
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// FIXME: Only GlobalAddress for now.
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GlobalValue *GV = dyn_cast<GlobalValue>(V);
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if (!GV)
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@ -308,7 +310,24 @@ bool X86FastISel::X86SelectConstAddr(Value *V, unsigned &Op0, bool isCall) {
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addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
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// Prevent loading GV stub multiple times in same MBB.
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LocalValueMap[V] = Op0;
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} else if (inReg) {
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::LEA32r;
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RC = X86::GR32RegisterClass;
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} else {
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Opc = X86::LEA64r;
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RC = X86::GR64RegisterClass;
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}
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Op0 = createResultReg(RC);
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X86AddressMode AM;
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AM.GV = GV;
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addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
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// Prevent materializing GV address multiple times in same MBB.
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LocalValueMap[V] = Op0;
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}
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return true;
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}
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@ -323,12 +342,17 @@ bool X86FastISel::X86SelectStore(Instruction* I) {
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return false;
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Value *V = I->getOperand(1);
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unsigned Ptr = getRegForValue(V);
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if (Ptr == 0) {
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// Handle constant store address.
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if (!isa<Constant>(V) || !X86SelectConstAddr(V, Ptr))
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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unsigned Ptr = lookUpRegForValue(V);
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if (!Ptr) {
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// Handle constant load address.
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// FIXME: If load type is something we can't handle, this can result in
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// a dead stub load instruction.
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if (!isa<Constant>(V) || !X86SelectConstAddr(V, Ptr)) {
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Ptr = getRegForValue(V);
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if (Ptr == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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}
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return X86FastEmitStore(VT, Val, Ptr, 0, V);
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@ -342,14 +366,17 @@ bool X86FastISel::X86SelectLoad(Instruction *I) {
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return false;
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Value *V = I->getOperand(0);
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unsigned Ptr = getRegForValue(V);
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if (Ptr == 0) {
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unsigned Ptr = lookUpRegForValue(V);
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if (!Ptr) {
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// Handle constant load address.
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// FIXME: If load type is something we can't handle, this can result in
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// a dead stub load instruction.
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if (!isa<Constant>(V) || !X86SelectConstAddr(V, Ptr))
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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if (!isa<Constant>(V) || !X86SelectConstAddr(V, Ptr)) {
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Ptr = getRegForValue(V);
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if (Ptr == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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}
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unsigned ResultReg = 0;
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@ -917,18 +944,8 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C,
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if (TM.getRelocationModel() == Reloc::PIC_)
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return 0;
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MVT VT = MVT::getMVT(C->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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if (VT == MVT::iPTR)
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// Use pointer type.
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VT = TLI.getPointerTy();
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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if (!TLI.isTypeLegal(VT))
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MVT VT;
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if (!isTypeLegal(C->getType(), TLI, VT))
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return false;
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// Get opcode and regclass of the output for the given load instruction.
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@ -979,9 +996,7 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C,
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unsigned ResultReg = createResultReg(RC);
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if (isa<GlobalValue>(C)) {
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// FIXME: If store value type is something we can't handle, this can result
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// in a dead stub load instruction.
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if (X86SelectConstAddr(C, ResultReg))
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if (X86SelectConstAddr(C, ResultReg, false, true))
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return ResultReg;
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return 0;
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}
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@ -1,5 +1,7 @@
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; RUN: llvm-as < %s | llc -fast-isel -mtriple=i386-apple-darwin -mattr=sse2 | \
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; RUN: grep mov | grep lazy_ptr | count 1
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; RUN: llvm-as < %s | llc -fast-isel -mtriple=i386-apple-darwin | \
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; RUN: grep mov | grep lazy_ptr | count 2
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; RUN: llvm-as < %s | llc -fast-isel -march=x86 -relocation-model=static | \
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; RUN: grep lea
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@src = external global i32
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@ -8,6 +10,15 @@ entry:
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%0 = load i32* @src, align 4
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%1 = load i32* @src, align 4
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%2 = add i32 %0, %1
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store i32 %2, i32* @src
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store i32 %2, i32* @src
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ret i32 %2
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}
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%stuff = type { i32 (...)** }
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@LotsStuff = external constant [4 x i32 (...)*]
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define void @t(%stuff* %this) nounwind {
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entry:
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store i32 (...)** getelementptr ([4 x i32 (...)*]* @LotsStuff, i32 0, i32 2), i32 (...)*** null, align 4
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ret void
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}
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