From 5a24ed951b7f5e553a7e4e1415da5be247db443e Mon Sep 17 00:00:00 2001
From: Justin Holewinski <jholewinski@nvidia.com>
Date: Fri, 26 Jul 2013 12:46:39 +0000
Subject: [PATCH] Add a target legalize hook for SplitVectorOperand

CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.

This also adds a test case for NVPTX that depends on this custom
legalization.

Differential Revision: http://llvm-reviews.chandlerc.com/D1195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187198 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../SelectionDAG/LegalizeVectorTypes.cpp      |  4 +++
 lib/Target/X86/X86ISelLowering.cpp            |  2 +-
 test/CodeGen/NVPTX/vector-stores.ll           | 30 +++++++++++++++++++
 test/CodeGen/X86/floor-soft-float.ll          | 11 +++++++
 4 files changed, 46 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/NVPTX/vector-stores.ll
 create mode 100644 test/CodeGen/X86/floor-soft-float.ll

diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 75bb6094f56..72c16b5d39e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1031,6 +1031,10 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
         dbgs() << "\n");
   SDValue Res = SDValue();
 
+  // See if the target wants to custom split this node.
+  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
+    return false;
+
   if (Res.getNode() == 0) {
     switch (N->getOpcode()) {
     default:
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index e75781e6ba0..ad2d30891ed 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -996,7 +996,7 @@ void X86TargetLowering::resetOperationActions() {
     setLoadExtAction(ISD::EXTLOAD,              MVT::v2f32, Legal);
   }
 
-  if (Subtarget->hasSSE41()) {
+  if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
     setOperationAction(ISD::FFLOOR,             MVT::f32,   Legal);
     setOperationAction(ISD::FCEIL,              MVT::f32,   Legal);
     setOperationAction(ISD::FTRUNC,             MVT::f32,   Legal);
diff --git a/test/CodeGen/NVPTX/vector-stores.ll b/test/CodeGen/NVPTX/vector-stores.ll
new file mode 100644
index 00000000000..49418122da5
--- /dev/null
+++ b/test/CodeGen/NVPTX/vector-stores.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+; CHECK: .visible .func foo1
+; CHECK: st.v2.f32
+define void @foo1(<2 x float> %val, <2 x float>* %ptr) {
+  store <2 x float> %val, <2 x float>* %ptr
+  ret void
+}
+
+; CHECK: .visible .func foo2
+; CHECK: st.v4.f32
+define void @foo2(<4 x float> %val, <4 x float>* %ptr) {
+  store <4 x float> %val, <4 x float>* %ptr
+  ret void
+}
+
+; CHECK: .visible .func foo3
+; CHECK: st.v2.u32
+define void @foo3(<2 x i32> %val, <2 x i32>* %ptr) {
+  store <2 x i32> %val, <2 x i32>* %ptr
+  ret void
+}
+
+; CHECK: .visible .func foo4
+; CHECK: st.v4.u32
+define void @foo4(<4 x i32> %val, <4 x i32>* %ptr) {
+  store <4 x i32> %val, <4 x i32>* %ptr
+  ret void
+}
+
diff --git a/test/CodeGen/X86/floor-soft-float.ll b/test/CodeGen/X86/floor-soft-float.ll
new file mode 100644
index 00000000000..158a82413d1
--- /dev/null
+++ b/test/CodeGen/X86/floor-soft-float.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse41 -soft-float=0 | FileCheck %s --check-prefix=CHECK-HARD-FLOAT
+; RUN: llc < %s -march=x86-64 -mattr=+sse41 -soft-float=1 | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT
+
+declare float @llvm.floor.f32(float)
+
+; CHECK-SOFT-FLOAT: callq _floorf
+; CHECK-HARD-FLOAT: vroundss $1, %xmm0, %xmm0, %xmm0
+define float @myfloor(float %a) {
+  %val = tail call float @llvm.floor.f32(float %a)
+  ret float %val
+}