6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

PTX: support for bitwise operations on predicates

Browse Source 
- selection of bitwise preds (AND, OR, XOR)
- new bitwise.ll test

Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130353 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski 2011-04-28 00:19:51 +00:00
parent 9583a86ba8
commit 5a3cb924c6
2 changed files with 32 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/PTX/PTXInstrInfo.td
View File

@ -258,6 +258,14 @@ multiclass INT3<string opcstr, SDNode opnode> {
}
multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
def ripreds : InstPTX<(outs Preds:$d),
(ins Preds:$a, i1imm:$b),
!strconcat(opcstr, ".pred\t$d, $a, $b"),
[(set Preds:$d, (opnode Preds:$a, imm:$b))]>;
def rrpreds : InstPTX<(outs Preds:$d),
(ins Preds:$a, Preds:$b),
!strconcat(opcstr, ".pred\t$d, $a, $b"),
[(set Preds:$d, (opnode Preds:$a, Preds:$b))]>;
def rr16 : InstPTX<(outs RRegu16:$d),
(ins RRegu16:$a, RRegu16:$b),
!strconcat(opcstr, ".b16\t$d, $a, $b"),

24
test/CodeGen/PTX/bitwise.ll Normal file
View File

@ -0,0 +1,24 @@
; RUN: llc < %s -march=ptx32 | FileCheck %s
; preds
define ptx_device i32 @t1_and_preds(i1 %x, i1 %y) {
; CHECK: and.pred p0, p1, p2
%c = and i1 %x, %y
%d = zext i1 %c to i32
ret i32 %d
}
define ptx_device i32 @t1_or_preds(i1 %x, i1 %y) {
; CHECK: or.pred p0, p1, p2
%a = or i1 %x, %y
%b = zext i1 %a to i32
ret i32 %b
}
define ptx_device i32 @t1_xor_preds(i1 %x, i1 %y) {
; CHECK: xor.pred p0, p1, p2
%a = xor i1 %x, %y
%b = zext i1 %a to i32
ret i32 %b
}