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Uncommented LR spill code insertion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1207 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
parent
3bc29389c5
commit
5a61d85f97
@ -437,8 +437,8 @@ void PhyRegAlloc::updateMachineCode()
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// LR did NOT receive a color (register). Now, insert spill code
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// for spilled opeands in this machine instruction
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assert(0 && "LR must be spilled");
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// insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
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//assert(0 && "LR must be spilled");
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insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
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}
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}
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@ -503,6 +503,89 @@ void PhyRegAlloc::updateMachineCode()
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}
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//----------------------------------------------------------------------------
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// This method inserts spill code for AN operand whose LR was spilled.
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// This method may be called several times for a single machine instruction
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// if it contains many spilled operands. Each time it is called, it finds
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// a register which is not live at that instruction and also which is not
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// used by other spilled operands of the same instruction. Then it uses
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// this register temporarily to accomodate the spilled value.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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MachineInstr *MInst,
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const BasicBlock *BB,
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const unsigned OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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bool isDef = MInst->operandIsDefined(OpNum);
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unsigned RegType = MRI.getRegType( LR );
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int SpillOff = LR->getSpillOffFromFP();
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RegClass *RC = LR->getRegClass();
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const LiveVarSet *LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
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int TmpOff =
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mcInfo.pushTempValue(TM, TM.findOptimalStorageSize(LR->getType()));
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MachineInstr *MIBef, *AdIMid, *MIAft;
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int TmpReg;
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TmpReg = getUsableRegAtMI(RC, RegType, MInst,LVSetBef, MIBef, MIAft);
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TmpReg = MRI.getUnifiedRegNum( RC->getID(), TmpReg );
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if( !isDef ) {
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// for a USE, we have to load the value of LR from stack to a TmpReg
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// and use the TmpReg as one operand of instruction
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// actual loading instruction
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AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpReg, RegType);
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if( MIBef )
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((AddedInstrMap[MInst])->InstrnsBefore).push_back(MIBef);
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((AddedInstrMap[MInst])->InstrnsBefore).push_back(AdIMid);
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if( MIAft)
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((AddedInstrMap[MInst])->InstrnsAfter).push_front(MIAft);
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}
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else { // if this is a Def
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// for a DEF, we have to store the value produced by this instruction
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// on the stack position allocated for this LR
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// actual storing instruction
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AdIMid = MRI.cpReg2MemMI(TmpReg, MRI.getFramePointer(), SpillOff, RegType);
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if( MIBef )
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((AddedInstrMap[MInst])->InstrnsBefore).push_back(MIBef);
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((AddedInstrMap[MInst])->InstrnsBefore).push_back(AdIMid);
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if( MIAft)
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((AddedInstrMap[MInst])->InstrnsAfter).push_front(MIAft);
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} // if !DEF
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cerr << "\nFor Inst " << *MInst;
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cerr << "\n - SPILLED LR:"; LR->printSet();
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cerr << "\n - Added Instructions:";
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if( MIBef ) cerr << *MIBef;
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cerr << *AdIMid;
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if( MIAft ) cerr << *MIAft;
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Op.setRegForValue( TmpReg ); // set the opearnd
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}
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//----------------------------------------------------------------------------
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// We can use the following method to get a temporary register to be used
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// BEFORE any given machine instruction. If there is a register available,
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@ -437,8 +437,8 @@ void PhyRegAlloc::updateMachineCode()
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// LR did NOT receive a color (register). Now, insert spill code
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// for spilled opeands in this machine instruction
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assert(0 && "LR must be spilled");
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// insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
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//assert(0 && "LR must be spilled");
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insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
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}
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}
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@ -503,6 +503,89 @@ void PhyRegAlloc::updateMachineCode()
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}
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//----------------------------------------------------------------------------
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// This method inserts spill code for AN operand whose LR was spilled.
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// This method may be called several times for a single machine instruction
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// if it contains many spilled operands. Each time it is called, it finds
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// a register which is not live at that instruction and also which is not
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// used by other spilled operands of the same instruction. Then it uses
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// this register temporarily to accomodate the spilled value.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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MachineInstr *MInst,
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const BasicBlock *BB,
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const unsigned OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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bool isDef = MInst->operandIsDefined(OpNum);
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unsigned RegType = MRI.getRegType( LR );
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int SpillOff = LR->getSpillOffFromFP();
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RegClass *RC = LR->getRegClass();
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const LiveVarSet *LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
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int TmpOff =
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mcInfo.pushTempValue(TM, TM.findOptimalStorageSize(LR->getType()));
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MachineInstr *MIBef, *AdIMid, *MIAft;
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int TmpReg;
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TmpReg = getUsableRegAtMI(RC, RegType, MInst,LVSetBef, MIBef, MIAft);
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TmpReg = MRI.getUnifiedRegNum( RC->getID(), TmpReg );
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if( !isDef ) {
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// for a USE, we have to load the value of LR from stack to a TmpReg
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// and use the TmpReg as one operand of instruction
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// actual loading instruction
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AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpReg, RegType);
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if( MIBef )
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((AddedInstrMap[MInst])->InstrnsBefore).push_back(MIBef);
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((AddedInstrMap[MInst])->InstrnsBefore).push_back(AdIMid);
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if( MIAft)
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((AddedInstrMap[MInst])->InstrnsAfter).push_front(MIAft);
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}
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else { // if this is a Def
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// for a DEF, we have to store the value produced by this instruction
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// on the stack position allocated for this LR
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// actual storing instruction
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AdIMid = MRI.cpReg2MemMI(TmpReg, MRI.getFramePointer(), SpillOff, RegType);
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if( MIBef )
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((AddedInstrMap[MInst])->InstrnsBefore).push_back(MIBef);
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((AddedInstrMap[MInst])->InstrnsBefore).push_back(AdIMid);
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if( MIAft)
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((AddedInstrMap[MInst])->InstrnsAfter).push_front(MIAft);
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} // if !DEF
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cerr << "\nFor Inst " << *MInst;
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cerr << "\n - SPILLED LR:"; LR->printSet();
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cerr << "\n - Added Instructions:";
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if( MIBef ) cerr << *MIBef;
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cerr << *AdIMid;
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if( MIAft ) cerr << *MIAft;
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Op.setRegForValue( TmpReg ); // set the opearnd
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}
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//----------------------------------------------------------------------------
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// We can use the following method to get a temporary register to be used
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// BEFORE any given machine instruction. If there is a register available,
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