6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-21 21:29:41 +00:00
Code Issues Projects Releases Wiki Activity

Implement special case for storing an immediate into memory so that we don't need

Browse Source 
an intermediate register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11816 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-25 02:56:58 +00:00
parent bb92f6fbf2
commit 5a83096d6a
2 changed files with 58 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
lib/Target/X86/InstSelectSimple.cpp
View File

@ -1907,24 +1907,40 @@ void ISel::visitLoadInst(LoadInst &I) {
/// instruction.
///
void ISel::visitStoreInst(StoreInst &I) {
unsigned ValReg = getReg(I.getOperand(0));
unsigned AddressReg = getReg(I.getOperand(1));
const Type *ValTy = I.getOperand(0)->getType();
unsigned Class = getClassB(ValTy);
if (Class == cLong) {
addDirectMem(BuildMI(BB, X86::MOVmr32, 1+4), AddressReg).addReg(ValReg);
addRegOffset(BuildMI(BB, X86::MOVmr32, 1+4), AddressReg,4).addReg(ValReg+1);
return;
if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
uint64_t Val = CI->getRawValue();
if (Class == cLong) {
addDirectMem(BuildMI(BB, X86::MOVmi32, 5), AddressReg).addZImm(Val & ~0U);
addRegOffset(BuildMI(BB, X86::MOVmi32, 5), AddressReg,4).addZImm(Val>>32);
} else {
static const unsigned Opcodes[] = {
X86::MOVmi8, X86::MOVmi16, X86::MOVmi32
};
unsigned Opcode = Opcodes[Class];
addDirectMem(BuildMI(BB, Opcode, 5), AddressReg).addZImm(Val);
}
} else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
addDirectMem(BuildMI(BB, X86::MOVmi8, 5),
AddressReg).addZImm(CB->getValue());
} else {
if (Class == cLong) {
unsigned ValReg = getReg(I.getOperand(0));
addDirectMem(BuildMI(BB, X86::MOVmr32, 5), AddressReg).addReg(ValReg);
addRegOffset(BuildMI(BB, X86::MOVmr32, 5), AddressReg,4).addReg(ValReg+1);
} else {
unsigned ValReg = getReg(I.getOperand(0));
static const unsigned Opcodes[] = {
X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTr32
};
unsigned Opcode = Opcodes[Class];
if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
}
}
static const unsigned Opcodes[] = {
X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTr32
};
unsigned Opcode = Opcodes[Class];
if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
}

42
lib/Target/X86/X86ISelSimple.cpp
View File

@ -1907,24 +1907,40 @@ void ISel::visitLoadInst(LoadInst &I) {
/// instruction.
///
void ISel::visitStoreInst(StoreInst &I) {
unsigned ValReg = getReg(I.getOperand(0));
unsigned AddressReg = getReg(I.getOperand(1));
const Type *ValTy = I.getOperand(0)->getType();
unsigned Class = getClassB(ValTy);
if (Class == cLong) {
addDirectMem(BuildMI(BB, X86::MOVmr32, 1+4), AddressReg).addReg(ValReg);
addRegOffset(BuildMI(BB, X86::MOVmr32, 1+4), AddressReg,4).addReg(ValReg+1);
return;
if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
uint64_t Val = CI->getRawValue();
if (Class == cLong) {
addDirectMem(BuildMI(BB, X86::MOVmi32, 5), AddressReg).addZImm(Val & ~0U);
addRegOffset(BuildMI(BB, X86::MOVmi32, 5), AddressReg,4).addZImm(Val>>32);
} else {
static const unsigned Opcodes[] = {
X86::MOVmi8, X86::MOVmi16, X86::MOVmi32
};
unsigned Opcode = Opcodes[Class];
addDirectMem(BuildMI(BB, Opcode, 5), AddressReg).addZImm(Val);
}
} else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
addDirectMem(BuildMI(BB, X86::MOVmi8, 5),
AddressReg).addZImm(CB->getValue());
} else {
if (Class == cLong) {
unsigned ValReg = getReg(I.getOperand(0));
addDirectMem(BuildMI(BB, X86::MOVmr32, 5), AddressReg).addReg(ValReg);
addRegOffset(BuildMI(BB, X86::MOVmr32, 5), AddressReg,4).addReg(ValReg+1);
} else {
unsigned ValReg = getReg(I.getOperand(0));
static const unsigned Opcodes[] = {
X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTr32
};
unsigned Opcode = Opcodes[Class];
if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
}
}
static const unsigned Opcodes[] = {
X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTr32
};
unsigned Opcode = Opcodes[Class];
if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
}