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Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -54,7 +54,7 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
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// Clear "do not change" set.
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KeepRegs.clear();
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bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
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bool IsReturnBlock = (!BB->empty() && BB->back().isReturn());
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// Determine the live-out physregs for this block.
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if (IsReturnBlock) {
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@@ -193,8 +193,8 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
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// instruction which may not be executed. The second R6 def may or may not
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// re-define R6 so it's not safe to change it since the last R6 use cannot be
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// changed.
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bool Special = MI->getDesc().isCall() ||
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MI->getDesc().hasExtraSrcRegAllocReq() ||
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bool Special = MI->isCall() ||
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MI->hasExtraSrcRegAllocReq() ||
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TII->isPredicated(MI);
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// Scan the register operands for this instruction and update
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@@ -572,7 +572,7 @@ BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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// If MI's defs have a special allocation requirement, don't allow
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// any def registers to be changed. Also assume all registers
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// defined in a call must not be changed (ABI).
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if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() ||
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if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
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TII->isPredicated(MI))
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// If this instruction's defs have special allocation requirement, don't
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// break this anti-dependency.
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