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Extend the (abi-irrelevant) return convention to be able to return more than two values in

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integer registers.  This is already supported by the fastcc convention, but it doesn't
hurt to support it in the standard conventions as well.

In cases where we can cheat at the calling convention, this allows us to avoid returning
things through memory in more cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157698 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2012-05-30 17:50:14 +00:00
parent ada759d5fa
commit 5aaabbfe62
2 changed files with 24 additions and 4 deletions
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11
lib/Target/X86/X86CallingConv.td
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@ -29,10 +29,13 @@ def RetCC_X86Common : CallingConv<[
// up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
// for functions that return two i8 values are currently expected to pack the
// values into an i16 (which uses AX, and thus AL:AH).
CCIfType<[i8] , CCAssignToReg<[AL, DL]>>,
CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
//
// For code that doesn't care about the ABI, we allow returning more than two
// integer values in registers.
CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R11]>>,
// Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
// can only be used by ABI non-compliant code. If the target doesn't have XMM

17
test/CodeGen/X86/pass-four.ll Normal file
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@ -0,0 +1,17 @@
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin11.3.0"
define { i8*, i64, i64*, i64 } @copy_4(i8* %a, i64 %b, i64* %c, i64 %d) nounwind {
entry:
%0 = insertvalue { i8*, i64, i64*, i64 } undef, i8* %a, 0
%1 = insertvalue { i8*, i64, i64*, i64 } %0, i64 %b, 1
%2 = insertvalue { i8*, i64, i64*, i64 } %1, i64* %c, 2
%3 = insertvalue { i8*, i64, i64*, i64 } %2, i64 %d, 3
ret { i8*, i64, i64*, i64 } %3
}
; CHECK: copy_4:
; CHECK-NOT: (%rdi)
; CHECK: ret