From 5aaddaa7b8d52eec58f6eec0a4a897a03b517ca4 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Sat, 8 Dec 2007 07:22:58 +0000
Subject: [PATCH] aesthetic changes, no functionality change.  Evan, it's not
 clear what 'Available' is, please add a comment near it and rename it if
 appropriate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44703 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelDAGToDAG.cpp | 78 +++++++++++++++---------------
 1 file changed, 40 insertions(+), 38 deletions(-)

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 73cecdb967e..35a5516c599 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -562,7 +562,7 @@ void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
 
 /// MatchAddress - Add the specified node to the specified addressing mode,
 /// returning true if it cannot be done.  This just pattern matches for the
-/// addressing mode
+/// addressing mode.
 bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
                                    bool isRoot, unsigned Depth) {
   // Limit recursion.
@@ -653,33 +653,35 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
     break;
 
   case ISD::SHL:
-    if (!Available && AM.IndexReg.Val == 0 && AM.Scale == 1)
-      if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
-        unsigned Val = CN->getValue();
-        if (Val == 1 || Val == 2 || Val == 3) {
-          AM.Scale = 1 << Val;
-          SDOperand ShVal = N.Val->getOperand(0);
+    if (Available || AM.IndexReg.Val != 0 || AM.Scale != 1)
+      break;
+      
+    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
+      unsigned Val = CN->getValue();
+      if (Val == 1 || Val == 2 || Val == 3) {
+        AM.Scale = 1 << Val;
+        SDOperand ShVal = N.Val->getOperand(0);
 
-          // Okay, we know that we have a scale by now.  However, if the scaled
-          // value is an add of something and a constant, we can fold the
-          // constant into the disp field here.
-          if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
-              isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
-            AM.IndexReg = ShVal.Val->getOperand(0);
-            ConstantSDNode *AddVal =
-              cast<ConstantSDNode>(ShVal.Val->getOperand(1));
-            uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
-            if (isInt32(Disp))
-              AM.Disp = Disp;
-            else
-              AM.IndexReg = ShVal;
-          } else {
+        // Okay, we know that we have a scale by now.  However, if the scaled
+        // value is an add of something and a constant, we can fold the
+        // constant into the disp field here.
+        if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
+            isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
+          AM.IndexReg = ShVal.Val->getOperand(0);
+          ConstantSDNode *AddVal =
+            cast<ConstantSDNode>(ShVal.Val->getOperand(1));
+          uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
+          if (isInt32(Disp))
+            AM.Disp = Disp;
+          else
             AM.IndexReg = ShVal;
-          }
-          return false;
+        } else {
+          AM.IndexReg = ShVal;
         }
+        return false;
       }
     break;
+    }
 
   case ISD::SMUL_LOHI:
   case ISD::UMUL_LOHI:
@@ -738,22 +740,22 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
 
   case ISD::OR:
     // Handle "X | C" as "X + C" iff X is known to have C bits clear.
-    if (!Available) {
-      if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
-        X86ISelAddressMode Backup = AM;
-        // Start with the LHS as an addr mode.
-        if (!MatchAddress(N.getOperand(0), AM, false) &&
-            // Address could not have picked a GV address for the displacement.
-            AM.GV == NULL &&
-            // On x86-64, the resultant disp must fit in 32-bits.
-            isInt32(AM.Disp + CN->getSignExtended()) &&
-            // Check to see if the LHS & C is zero.
-            CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
-          AM.Disp += CN->getValue();
-          return false;
-        }
-        AM = Backup;
+    if (Available) break;
+      
+    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+      X86ISelAddressMode Backup = AM;
+      // Start with the LHS as an addr mode.
+      if (!MatchAddress(N.getOperand(0), AM, false) &&
+          // Address could not have picked a GV address for the displacement.
+          AM.GV == NULL &&
+          // On x86-64, the resultant disp must fit in 32-bits.
+          isInt32(AM.Disp + CN->getSignExtended()) &&
+          // Check to see if the LHS & C is zero.
+          CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
+        AM.Disp += CN->getValue();
+        return false;
       }
+      AM = Backup;
     }
     break;
   }