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Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37118 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -278,7 +278,7 @@ def addrmodepc : Operand<i32>,
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}
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// ARM branch / cmov condition code operand.
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def ccop : PredicateOperand<i32, (ops i32imm), (ops)> {
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def ccop : Operand<i32> {
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let PrintMethod = "printPredicateOperand";
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}
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@ -364,7 +364,7 @@ class PseudoInst<dag ops, string asm, list<dag> pattern>
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let Pattern = pattern;
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}
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// Almost all ARM instructions are predicatable.
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// Almost all ARM instructions are predicable.
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class I<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
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string opc, string asm, string cstr, list<dag> pattern>
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// FIXME: Set all opcodes to 0 for now.
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@ -591,10 +591,11 @@ let isCall = 1, noResults = 1,
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}
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let isBranch = 1, isTerminator = 1, noResults = 1 in {
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// B can changed into a Bcc, but it is not "predicated".
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// B is "predicable" since it can be xformed into a Bcc.
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let isBarrier = 1 in {
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def B : AXI<(ops brtarget:$dst), "b $dst",
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[(br bb:$dst)]>;
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let isPredicable = 1 in
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def B : AXI<(ops brtarget:$dst), "b $dst",
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[(br bb:$dst)]>;
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def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
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"mov", " pc, $dst \n$jt",
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