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Add support for FP prefixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5151 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -209,9 +209,9 @@ unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
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case X86II::Arg8: return 1;
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case X86II::Arg8: return 1;
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case X86II::Arg16: return 2;
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case X86II::Arg16: return 2;
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case X86II::Arg32: return 4;
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case X86II::Arg32: return 4;
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case X86II::Arg64: return 8;
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case X86II::ArgF32: return 4;
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case X86II::Arg80: return 10;
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case X86II::ArgF64: return 8;
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case X86II::Arg128: return 16;
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case X86II::ArgF80: return 10;
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default: assert(0 && "Memory size not set!");
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default: assert(0 && "Memory size not set!");
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return 0;
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return 0;
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}
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}
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@ -224,10 +224,25 @@ void Emitter::emitInstruction(MachineInstr &MI) {
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// Emit instruction prefixes if neccesary
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// Emit instruction prefixes if neccesary
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
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if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix
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switch (Desc.TSFlags & X86II::Op0Mask) {
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case X86II::TB:
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MCE.emitByte(0x0F); // Two-byte opcode prefix
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break;
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case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
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case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
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MCE.emitByte(0xD8 + (Desc.TSFlags & X86II::Op0Mask)-X86II::D8);
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break; // Two-byte opcode prefix
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default: break; // No prefix!
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}
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unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode);
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unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode);
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switch (Desc.TSFlags & X86II::FormMask) {
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switch (Desc.TSFlags & X86II::FormMask) {
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default: assert(0 && "Unknown FormMask value!");
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case X86II::Pseudo:
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std::cerr << "X86 Machine Code Emitter: Not emitting: " << MI;
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break;
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case X86II::RawFrm:
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case X86II::RawFrm:
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MCE.emitByte(BaseOpcode);
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MCE.emitByte(BaseOpcode);
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@ -209,9 +209,9 @@ unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
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case X86II::Arg8: return 1;
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case X86II::Arg8: return 1;
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case X86II::Arg16: return 2;
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case X86II::Arg16: return 2;
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case X86II::Arg32: return 4;
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case X86II::Arg32: return 4;
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case X86II::Arg64: return 8;
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case X86II::ArgF32: return 4;
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case X86II::Arg80: return 10;
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case X86II::ArgF64: return 8;
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case X86II::Arg128: return 16;
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case X86II::ArgF80: return 10;
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default: assert(0 && "Memory size not set!");
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default: assert(0 && "Memory size not set!");
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return 0;
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return 0;
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}
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}
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@ -224,10 +224,25 @@ void Emitter::emitInstruction(MachineInstr &MI) {
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// Emit instruction prefixes if neccesary
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// Emit instruction prefixes if neccesary
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
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if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix
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switch (Desc.TSFlags & X86II::Op0Mask) {
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case X86II::TB:
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MCE.emitByte(0x0F); // Two-byte opcode prefix
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break;
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case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
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case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
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MCE.emitByte(0xD8 + (Desc.TSFlags & X86II::Op0Mask)-X86II::D8);
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break; // Two-byte opcode prefix
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default: break; // No prefix!
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}
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unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode);
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unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode);
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switch (Desc.TSFlags & X86II::FormMask) {
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switch (Desc.TSFlags & X86II::FormMask) {
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default: assert(0 && "Unknown FormMask value!");
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case X86II::Pseudo:
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std::cerr << "X86 Machine Code Emitter: Not emitting: " << MI;
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break;
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case X86II::RawFrm:
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case X86II::RawFrm:
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MCE.emitByte(BaseOpcode);
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MCE.emitByte(BaseOpcode);
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