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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130046 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2011-04-23 03:24:11 +00:00
parent f5af6ada3b
commit 5adfba283d
2 changed files with 8 additions and 8 deletions
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12
lib/Target/ARM/ARMISelLowering.h
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@ -88,7 +88,7 @@ namespace llvm {
MEMBARRIER_MCR, // Memory barrier (MCR) MEMBARRIER_MCR, // Memory barrier (MCR)
PRELOAD, // Preload PRELOAD, // Preload
VCEQ, // Vector compare equal. VCEQ, // Vector compare equal.
VCEQZ, // Vector compare equal to zero. VCEQZ, // Vector compare equal to zero.
VCGE, // Vector compare greater than or equal. VCGE, // Vector compare greater than or equal.
@ -173,7 +173,7 @@ namespace llvm {
// Bit-field insert // Bit-field insert
BFI, BFI,
// Vector OR with immediate // Vector OR with immediate
VORRIMM, VORRIMM,
// Vector AND with NOT of immediate // Vector AND with NOT of immediate
@ -408,7 +408,7 @@ namespace llvm {
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) const; const ARMSubtarget *ST) const;
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
@ -486,14 +486,14 @@ namespace llvm {
unsigned BinOpcode) const; unsigned BinOpcode) const;
}; };
enum NEONModImmType { enum NEONModImmType {
VMOVModImm, VMOVModImm,
VMVNModImm, VMVNModImm,
OtherModImm OtherModImm
}; };
namespace ARM { namespace ARM {
FastISel *createFastISel(FunctionLoweringInfo &funcInfo); FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
} }

4
test/CodeGen/Thumb2/thumb2-sbc.ll
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@ -39,7 +39,7 @@ define i64 @f5(i64 %a) {
; CHECK: f5 ; CHECK: f5
; CHECK: subs r0, #2 ; CHECK: subs r0, #2
; CHECK: adc r1, r1, #-1448498775 ; CHECK: adc r1, r1, #-1448498775
%tmp = sub i64 %a, 6221254862626095106 %tmp = sub i64 %a, 6221254862626095106
ret i64 %tmp ret i64 %tmp
} }
@ -48,7 +48,7 @@ define i64 @f6(i64 %a) {
; CHECK: f6 ; CHECK: f6
; CHECK: subs r0, #2 ; CHECK: subs r0, #2
; CHECK: sbc r1, r1, #66846720 ; CHECK: sbc r1, r1, #66846720
%tmp = sub i64 %a, 287104476244869122 %tmp = sub i64 %a, 287104476244869122
ret i64 %tmp ret i64 %tmp
} }