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Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS,

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whenever AVX is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138849 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-08-31 03:04:09 +00:00
parent 0899f5c62d
commit 5affa5196f
2 changed files with 16 additions and 6 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
View File

@ -11215,7 +11215,9 @@ X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
if (!(Op.isReg() && Op.isImplicit()))
MIB.addOperand(Op);
}
BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
BuildMI(*BB, MI, dl,
TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
MI->getOperand(0).getReg())
.addReg(X86::XMM0);
MI->eraseFromParent();
@ -11570,6 +11572,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
MBB->addSuccessor(EndMBB);
}
unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
// In the XMM save block, save all the XMM argument registers.
for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
@ -11578,7 +11581,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
MachineMemOperand::MOStore,
/*Size=*/16, /*Align=*/16);
BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
.addFrameIndex(RegSaveFrameIndex)
.addImm(/*Scale=*/1)
.addReg(/*IndexReg=*/0)

15
lib/Target/X86/X86InstrInfo.cpp
View File

@ -1959,7 +1959,8 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
else
Opc = X86::MOV8rr;
} else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Opc = X86::MOVAPSrr;
Opc = TM.getSubtarget<X86Subtarget>().hasAVX() ?
X86::VMOVAPSrr : X86::MOVAPSrr;
else if (X86::VR256RegClass.contains(DestReg, SrcReg))
Opc = X86::VMOVAPSYrr;
else if (X86::VR64RegClass.contains(DestReg, SrcReg))
@ -2044,13 +2045,19 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
case 10:
assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
return load ? X86::LD_Fp80m : X86::ST_FpP80m;
case 16:
case 16: {
assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
// If stack is realigned we can use aligned stores.
if (isStackAligned)
return load ? X86::MOVAPSrm : X86::MOVAPSmr;
return load ?
(HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
(HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
else
return load ? X86::MOVUPSrm : X86::MOVUPSmr;
return load ?
(HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
(HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
}
case 32:
assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
// If stack is realigned we can use aligned stores.