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Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS,
whenever AVX is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138849 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -11215,7 +11215,9 @@ X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
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if (!(Op.isReg() && Op.isImplicit()))
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if (!(Op.isReg() && Op.isImplicit()))
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MIB.addOperand(Op);
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MIB.addOperand(Op);
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}
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}
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BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
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BuildMI(*BB, MI, dl,
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TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
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MI->getOperand(0).getReg())
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.addReg(X86::XMM0);
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.addReg(X86::XMM0);
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MI->eraseFromParent();
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MI->eraseFromParent();
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@ -11570,6 +11572,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
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MBB->addSuccessor(EndMBB);
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MBB->addSuccessor(EndMBB);
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}
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}
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unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
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// In the XMM save block, save all the XMM argument registers.
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// In the XMM save block, save all the XMM argument registers.
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for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
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for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
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int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
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int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
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@ -11578,7 +11581,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
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MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
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MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
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MachineMemOperand::MOStore,
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MachineMemOperand::MOStore,
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/*Size=*/16, /*Align=*/16);
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/*Size=*/16, /*Align=*/16);
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BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
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BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
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.addFrameIndex(RegSaveFrameIndex)
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.addFrameIndex(RegSaveFrameIndex)
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.addImm(/*Scale=*/1)
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.addImm(/*Scale=*/1)
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.addReg(/*IndexReg=*/0)
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.addReg(/*IndexReg=*/0)
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@ -1959,7 +1959,8 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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else
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else
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Opc = X86::MOV8rr;
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Opc = X86::MOV8rr;
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} else if (X86::VR128RegClass.contains(DestReg, SrcReg))
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} else if (X86::VR128RegClass.contains(DestReg, SrcReg))
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Opc = X86::MOVAPSrr;
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Opc = TM.getSubtarget<X86Subtarget>().hasAVX() ?
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X86::VMOVAPSrr : X86::MOVAPSrr;
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else if (X86::VR256RegClass.contains(DestReg, SrcReg))
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else if (X86::VR256RegClass.contains(DestReg, SrcReg))
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Opc = X86::VMOVAPSYrr;
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Opc = X86::VMOVAPSYrr;
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else if (X86::VR64RegClass.contains(DestReg, SrcReg))
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else if (X86::VR64RegClass.contains(DestReg, SrcReg))
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@ -2044,13 +2045,19 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
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case 10:
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case 10:
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assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
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assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
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return load ? X86::LD_Fp80m : X86::ST_FpP80m;
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return load ? X86::LD_Fp80m : X86::ST_FpP80m;
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case 16:
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case 16: {
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assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
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assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
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bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
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// If stack is realigned we can use aligned stores.
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// If stack is realigned we can use aligned stores.
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if (isStackAligned)
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if (isStackAligned)
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return load ? X86::MOVAPSrm : X86::MOVAPSmr;
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return load ?
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(HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
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(HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
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else
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else
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return load ? X86::MOVUPSrm : X86::MOVUPSmr;
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return load ?
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(HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
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(HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
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}
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case 32:
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case 32:
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assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
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assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
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// If stack is realigned we can use aligned stores.
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// If stack is realigned we can use aligned stores.
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