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Handle ARM inline asm "w" constraints with 64-bit ("d") registers.

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The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-12-18 01:03:29 +00:00
parent f042396b0f
commit 5afffaed5c
3 changed files with 15 additions and 3 deletions
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2
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -443,7 +443,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
// Vector ValueVT.
if (NumParts == 1) {
if (PartVT != ValueVT) {
if (PartVT.isVector()) {
if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
} else {
assert(ValueVT.getVectorElementType() == PartVT &&

4
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -4265,7 +4265,7 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
case 'w':
if (VT == MVT::f32)
return std::make_pair(0U, ARM::SPRRegisterClass);
if (VT == MVT::f64)
if (VT.getSizeInBits() == 64)
return std::make_pair(0U, ARM::DPRRegisterClass);
if (VT.getSizeInBits() == 128)
return std::make_pair(0U, ARM::QPRRegisterClass);
@ -4302,7 +4302,7 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
ARM::S20,ARM::S21,ARM::S22,ARM::S23,
ARM::S24,ARM::S25,ARM::S26,ARM::S27,
ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
if (VT == MVT::f64)
if (VT.getSizeInBits() == 64)
return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
ARM::D4, ARM::D5, ARM::D6, ARM::D7,
ARM::D8, ARM::D9, ARM::D10,ARM::D11,

12
test/CodeGen/ARM/inlineasm3.ll
View File

@ -1,5 +1,6 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
; Radar 7449043
%struct.int32x4_t = type { <4 x i32> }
define arm_apcscc void @t() nounwind {
@ -11,3 +12,14 @@ entry:
call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind
ret void
}
; Radar 7457110
%struct.int32x2_t = type { <4 x i32> }
define arm_apcscc void @t2() nounwind {
entry:
; CHECK: vmov d30, d0
; CHECK: vmov.32 r0, d30[0]
%asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind
ret void
}