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ARM64: make sure FastISel uses a GPR64 source in 64-bit extensions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207620 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
2014-04-30 09:32:01 +00:00
parent 6253c04fc9
commit 5b188b1cb8
2 changed files with 43 additions and 8 deletions
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9
lib/Target/ARM64/ARM64FastISel.cpp
View File

@@ -1746,6 +1746,15 @@ unsigned ARM64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
// Handle i8 and i16 as i32. // Handle i8 and i16 as i32.
if (DestVT == MVT::i8 || DestVT == MVT::i16) if (DestVT == MVT::i8 || DestVT == MVT::i16)
DestVT = MVT::i32; DestVT = MVT::i32;
else if (DestVT == MVT::i64) {
unsigned Src64 = MRI.createVirtualRegister(&ARM64::GPR64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(ARM64::SUBREG_TO_REG), Src64)
.addImm(0)
.addReg(SrcReg)
.addImm(ARM64::sub_32);
SrcReg = Src64;
}
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)

42
test/CodeGen/ARM64/fast-isel-conversion.ll
View File

@@ -57,7 +57,8 @@ entry:
; CHECK: uxth w0, w0 ; CHECK: uxth w0, w0
; CHECK: str w0, [sp, #8] ; CHECK: str w0, [sp, #8]
; CHECK: ldr w0, [sp, #8] ; CHECK: ldr w0, [sp, #8]
; CHECK: ubfx x3, w0, #0, #32 ; CHECK: mov x3, x0
; CHECK: ubfx x3, x3, #0, #32
; CHECK: str x3, [sp] ; CHECK: str x3, [sp]
; CHECK: ldr x0, [sp], #16 ; CHECK: ldr x0, [sp], #16
; CHECK: ret ; CHECK: ret
@@ -113,7 +114,8 @@ entry:
; CHECK: sxth w0, w0 ; CHECK: sxth w0, w0
; CHECK: str w0, [sp, #8] ; CHECK: str w0, [sp, #8]
; CHECK: ldr w0, [sp, #8] ; CHECK: ldr w0, [sp, #8]
; CHECK: sxtw x3, w0 ; CHECK: mov x3, x0
; CHECK: sxtw x3, w3
; CHECK: str x3, [sp] ; CHECK: str x3, [sp]
; CHECK: ldr x0, [sp], #16 ; CHECK: ldr x0, [sp], #16
; CHECK: ret ; CHECK: ret
@@ -139,12 +141,21 @@ entry:
} }
; Test sext i8 to i64 ; Test sext i8 to i64
define i64 @sext_2(i8 signext %a) nounwind ssp {
entry: define zeroext i64 @sext_i8_i64(i8 zeroext %in) {
; CHECK: sext_2 ; CHECK-LABEL: sext_i8_i64:
; CHECK: sxtb x0, w0 ; CHECK: mov x[[TMP:[0-9]+]], x0
%conv = sext i8 %a to i64 ; CHECK: sxtb x0, w[[TMP]]
ret i64 %conv %big = sext i8 %in to i64
ret i64 %big
}
define zeroext i64 @sext_i16_i64(i16 zeroext %in) {
; CHECK-LABEL: sext_i16_i64:
; CHECK: mov x[[TMP:[0-9]+]], x0
; CHECK: sxth x0, w[[TMP]]
%big = sext i16 %in to i64
ret i64 %big
} }
; Test sext i1 to i32 ; Test sext i1 to i32
@@ -414,3 +425,18 @@ define void @stack_trunc() nounwind {
store i8 %d, i8* %a, align 1 store i8 %d, i8* %a, align 1
ret void ret void
} }
define zeroext i64 @zext_i8_i64(i8 zeroext %in) {
; CHECK-LABEL: zext_i8_i64:
; CHECK: mov x[[TMP:[0-9]+]], x0
; CHECK: ubfx x0, x[[TMP]], #0, #8
%big = zext i8 %in to i64
ret i64 %big
}
define zeroext i64 @zext_i16_i64(i16 zeroext %in) {
; CHECK-LABEL: zext_i16_i64:
; CHECK: mov x[[TMP:[0-9]+]], x0
; CHECK: ubfx x0, x[[TMP]], #0, #16
%big = zext i16 %in to i64
ret i64 %big
}