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Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -9426,6 +9426,10 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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}
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// Arithmetic intrinsics.
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case Intrinsic::x86_sse2_pmulu_dq:
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case Intrinsic::x86_avx2_pmulu_dq:
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return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::x86_sse3_hadd_ps:
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case Intrinsic::x86_sse3_hadd_pd:
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case Intrinsic::x86_avx_hadd_ps_256:
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@ -10085,78 +10089,46 @@ SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
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if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
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return Lower256IntArith(Op, DAG);
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assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
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"Only know how to lower V2I64/V4I64 multiply");
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DebugLoc dl = Op.getDebugLoc();
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// Ahi = psrlqi(a, 32);
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// Bhi = psrlqi(b, 32);
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//
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// AloBlo = pmuludq(a, b);
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// AloBhi = pmuludq(a, Bhi);
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// AhiBlo = pmuludq(Ahi, b);
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// AloBhi = psllqi(AloBhi, 32);
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// AhiBlo = psllqi(AhiBlo, 32);
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// return AloBlo + AloBhi + AhiBlo;
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SDValue A = Op.getOperand(0);
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SDValue B = Op.getOperand(1);
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if (VT == MVT::v4i64) {
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assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
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SDValue ShAmt = DAG.getConstant(32, MVT::i32);
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// ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
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// ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
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// ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
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// ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
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// ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
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//
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// AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
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// AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
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// return AloBlo + AloBhi + AhiBlo;
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SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
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SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
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SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
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DAG.getConstant(32, MVT::i32));
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SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
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DAG.getConstant(32, MVT::i32));
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SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
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A, B);
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SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
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A, Bhi);
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SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
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Ahi, B);
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AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
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DAG.getConstant(32, MVT::i32));
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AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
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DAG.getConstant(32, MVT::i32));
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SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
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Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
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return Res;
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}
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// Bit cast to 32-bit vectors for MULUDQ
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EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
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A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
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B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
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Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
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Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
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assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
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SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
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SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
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SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
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// ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
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// ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
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// ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
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// ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
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// ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
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//
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// AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
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// AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
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// return AloBlo + AloBhi + AhiBlo;
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AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
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AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
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SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
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DAG.getConstant(32, MVT::i32));
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SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
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DAG.getConstant(32, MVT::i32));
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SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
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A, B);
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SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
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A, Bhi);
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SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
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Ahi, B);
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AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
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DAG.getConstant(32, MVT::i32));
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AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
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DAG.getConstant(32, MVT::i32));
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SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
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Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
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return Res;
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return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
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}
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SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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@ -11092,6 +11064,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
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case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
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case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
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case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
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case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
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case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
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case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
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@ -219,7 +219,7 @@ namespace llvm {
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// VZEXT_MOVL - Vector move low and zero extend.
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VZEXT_MOVL,
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// VZEXT_MOVL - Vector move low and sign extend.
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// VSEXT_MOVL - Vector move low and sign extend.
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VSEXT_MOVL,
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// VSHL, VSRL - 128-bit vector logical left / right shift
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@ -283,6 +283,9 @@ namespace llvm {
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VPERM2X128,
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VBROADCAST,
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// PMULUDQ - Vector multiply packed unsigned doubleword integers
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PMULUDQ,
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// VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
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// according to %al. An operator is needed so that this can be expanded
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// with control flow.
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@ -109,6 +109,10 @@ def X86vpcomu : SDNode<"X86ISD::VPCOMU",
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SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>>;
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def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisSameAs<1,2>]>>;
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// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
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// translated into one of the target nodes below during lowering.
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// Note: this is a work in progress...
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@ -3530,6 +3530,26 @@ multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
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[(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))]>;
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}
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/// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
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multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType DstVT, ValueType SrcVT, RegisterClass RC,
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PatFrag memop_frag, X86MemOperand x86memop,
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bit IsCommutable = 0, bit Is2Addr = 1> {
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let isCommutable = IsCommutable in
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def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
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def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
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(bitconvert (memop_frag addr:$src2)))))]>;
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}
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} // ExeDomain = SSEPackedInt
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// 128-bit Integer Arithmetic
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@ -3553,6 +3573,8 @@ defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
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i128mem, 0, 0>, VEX_4V;
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defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
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i128mem, 0, 0>, VEX_4V;
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defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
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memopv2i64, i128mem, 1, 0>, VEX_4V;
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// Intrinsic forms
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defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
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@ -3575,8 +3597,6 @@ defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
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VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
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defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
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VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
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defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq,
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VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
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defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
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VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
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defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
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@ -3614,6 +3634,8 @@ defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
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i256mem, 0, 0>, VEX_4V;
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defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
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i256mem, 0, 0>, VEX_4V;
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defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
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VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
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// Intrinsic forms
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defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
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@ -3636,8 +3658,6 @@ defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
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VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
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defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
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VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
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defm VPMULUDQY : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_avx2_pmulu_dq,
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VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
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defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
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VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
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defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
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@ -3675,6 +3695,8 @@ defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
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i128mem>;
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defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
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i128mem>;
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defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
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memopv2i64, i128mem, 1>;
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// Intrinsic forms
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defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
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@ -3697,8 +3719,6 @@ defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
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VR128, memopv2i64, i128mem, 1>;
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defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
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VR128, memopv2i64, i128mem, 1>;
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defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq,
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VR128, memopv2i64, i128mem, 1>;
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defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
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VR128, memopv2i64, i128mem, 1>;
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defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
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