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Fix pr11193.

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SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142724 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2011-10-22 12:39:25 +00:00
parent b8dcb314f7
commit 5b2bba6122
2 changed files with 15 additions and 3 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
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@ -10146,9 +10146,6 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG)
DAG.getConstant(SHLIntrinsicsID, MVT::i32),
Node->getOperand(0), ShAmt);
// In case of 1 bit sext, no need to shr
if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(SRAIntrinsicsID, MVT::i32),
Tmp1, ShAmt);

15
test/CodeGen/X86/2011-10-21-widen-cmp.ll
View File

@ -28,3 +28,18 @@ entry:
store <2 x double> %1, <2 x double>* undef
ret void
}
; CHECK: mp_11193
; CHECK: psraw $15
; CHECK: ret
define void @mp_11193(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET)
nounwind {
allocas:
%bincmp = fcmp olt <8 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 9.000000e+00, float 1.000000e+00, float 9.000000e+00, float 1.000000e+00> , <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>
%t = extractelement <8 x i1> %bincmp, i32 0
%ft = sitofp i1 %t to float
%pp = bitcast <8 x float>* %RET to float*
store float %ft, float* %pp
ret void
}