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Spill DPair registers, not just QPR.
The arm_neon intrinsics can create virtual registers from the DPair register class which allows both even-odd and odd-even D-register pairs. This fixes PR12389. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153603 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -757,7 +757,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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llvm_unreachable("Unknown reg class!");
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break;
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case 16:
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if (ARM::QPRRegClass.hasSubClassEq(RC)) {
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if (ARM::DPairRegClass.hasSubClassEq(RC)) {
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// Use aligned spills if the stack can be realigned.
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
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@ -907,7 +907,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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llvm_unreachable("Unknown reg class!");
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break;
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case 16:
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if (ARM::QPRRegClass.hasSubClassEq(RC)) {
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if (ARM::DPairRegClass.hasSubClassEq(RC)) {
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
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.addFrameIndex(FI).addImm(16)
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@ -530,16 +530,16 @@ def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
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// Use VLDM to load a Q register as a D register pair.
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// This is a pseudo instruction that is expanded to VLDMD after reg alloc.
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def VLDMQIA
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: PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
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: PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
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IIC_fpLoad_m, "",
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[(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
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[(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
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// Use VSTM to store a Q register as a D register pair.
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// This is a pseudo instruction that is expanded to VSTMD after reg alloc.
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def VSTMQIA
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: PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
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: PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
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IIC_fpStore_m, "",
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[(store (v2f64 QPR:$src), GPR:$Rn)]>;
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[(store (v2f64 DPair:$src), GPR:$Rn)]>;
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// Classes for VLD* pseudo-instructions with multi-register operands.
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// These are expanded to real instructions after register allocation.
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -verify-machineinstrs
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
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target triple = "thumbv7-apple-darwin10"
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@ -47,3 +47,17 @@ bb2: ; preds = %bb
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tail call void @llvm.arm.neon.vst4.v4i32(i8* bitcast ([16 x i32]* @dbuf to i8*), <4 x i32> %2, <4 x i32> %3, <4 x i32> %4, <4 x i32> %5, i32 1) nounwind
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ret i32 0
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}
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; PR12389
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; Make sure the DPair register class can spill.
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define void @pr12389(i8* %p) nounwind ssp {
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entry:
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%vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %p, i32 1)
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tail call void asm sideeffect "", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15}"() nounwind
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tail call void @llvm.arm.neon.vst1.v4f32(i8* %p, <4 x float> %vld1, i32 1)
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ret void
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}
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declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
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@ -569,6 +569,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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REG("DPR");
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REG("DPR_VFP2");
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REG("DPR_8");
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REG("DPair");
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REG("SPR");
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REG("QPR");
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REG("QQPR");
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